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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 26/46頁 |
| 文件大小： | 464K |
| 代理商： | MK68564 |
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cause the transmitted CRC character is inverted.
The final check must be 0001110100001111. he 2-
byteCRC check characters should be read and dis-
carded by theCPU, because the last two bits of the
2-byte SDLC CRC check characters are not trans-
ferred to the receive data FIFO due to the internal
timing associated with detecting the closing flag.
Unlike Synchronous modes, the logic path inSDLC
modedoesnothave an8-bitdelay betweenthetime
a character is transferred to the receive data FIFO
and the time a character enters the CRC checker.
Thisdelay isnotneeded, because in SDLC,all char-
actersbetweentheopening andclosingflags arein-
cluded in the CRC calculations. When the second
CRC character (six bits only) is loaded into the re-
ceive buffer, CRC calculation is complete.
SDLCReceiveTermination
. AnSDLCframeis ter-
minated when the closing flag is detected. The de-
tectionoftheflagsetstheEndOfFramebitinStatus
Register 1 and generates a Special Receive Condi-
tion Interrupt. In addition to the End Of Frame bit
beingset and the results of theCRC check, Status
Register 1 has three bits of Residue code valid at
this time. The Residue bits indicate the boundary
betweentheCRCcheckbitsandtheI-fieldbitsinthe
frame. A detailed description of the Residue code
bits is given in the Register Description section, un-
der Status Register 1.
Anyframe can be prematurely aborted by an Abort
sequence. Aborts are detected if seven or more
continuous ones occur in thereceived data stream.
This condition will cause an External/Status Inter-
ruptto be generated with theBreak/Abort bit in Sta-
tus Register 0 set. After the Reset External/Status
Interrupts command has been issued,a second in-
terrupt will occur when the continuous ones condi-
tion hasbeen cleared. Thissecond interrupt can be
used to distinguish between the Abort and Idle line
conditions.
REGISTER DESCRIPTION
The following sections describe the MK68564 SIO
registers. Each register is detailed in terms of bit
configuration, the active states ofeach bit, their de-
finitions, their functions, and their effects upon the
internal hardware and external pins.
COMMAND REGISTER (CMDREG)
Thisregister contains command and resetfunctions
D7
CRC
1
D6
CRC
0
D5
CMD
2
D4
CMD
1
D3
CMD
0
D2
D1
D0
LOOP
MODE
D7, D6 : Reset Codes 1 and 0
CRC 1
0
0
1
1
CRC 0
0
1
0
1
Null Code (no effect)
Reset Receiver CRC Checker
Reset Transmit CRC Generator
Reset Tx Underrun/End of
Message Latch
Null Code.
The null code has no effect on the
MK68564 SIO. It is used when writing to the
Command Register for some reason other than a
CRC Reset.
Reset Receiver CRC Checker.
It is necessary in
Synchronous modes(except SDLC) to reset the re-
ceiver CRC circuitry between received messages.
The CRC circuitry may be reset by one of the follo-
wing : disabling the receiver, setting the Enter Hunt
Modebitin theReceiver Control Register, orissuing
this Reset command. The CRC circuitry is reset
automatically in SDLC mode when the End Of
Frameflagisdetected.This Resetcommand willini-
tialize the CRC checker circuit to all ones in SDLC
mode and all zeros in the other Synchronous
modes.
Reset Transmit CRC Generator
. This command
resetsthe CRCgenerator toall ones in SDLCmode
and all zeros intheother Synchronous modes. This
command should be issued after the transmitter is
enabled but before the first character of a message
is loaded inthe transmit buffer.
Reset Transmit Underrun/EOM Latch
. This
commandresets the Underrun/EOM latch in Status
Register 0 if the transmitter is enabled. The Under-
run/EOMlatch controls the transmission of CRCat
theendofamessageinSynchronousmodes.When
a transmit underrun occurs and this latch is low,
CRC will be appended to the end of the transmis-
sion.
used inthe programming of theSIO. Thisregister is
reset to ”00H” by a channel or hardware reset. All
bits,exceptLoop Mode,willbereadas zeros during
a read cycle.
MK68564
26/46
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