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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 12/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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DMA Transfer
TheSIOprovides twooutput signalsperchannel for
connection to a DMA controller ; they are TxRDY
and RxRDY. The outputs are enabled under soft-
ware control by writing to the Interrupt Control Re-
gister. Both outputs willpulse Low for three system
clock cycles when their input conditions are active.
TxRDYwill be activewhen the Transmit Buffer
becomesempty. RxRDYwillbe active when achar-
acter is available in theReceive Buffer. If a Special
Receive Condition occurs when Interrupt On First
Character Only mode is selected, a receiver inter-
rupt will be generated and RxRDY willnot become
active. This will automatically inform the CPU of a
discrepancy in the data transfer.
nal/status logiclatches the current stateof allfivein-
put conditions, and generates an interrupt. To reini-
tialize the external/status logic to detect another
transition,
a
Reset
External/Status
command must be issued. The Break/Abort condi-
tionallowsthe SIO togenerate aninterrupt whenthe
Break/Abort sequence is detectedand terminated.
This feature facilitates the proper termination ofthe
current message, correct initialization of the next
message, and the accurate timing of the Break/A-
bortcondition inexternal logic.
Interrupts
SELFTEST
Whenthe Loop Mode bitissetintheCommandRe-
gister,thereceiver shiftclockinputpin(RxC)and the
receiver data input pin (RxD) are electrically dis-
connected from the internal logic. The transmit data
output pin (TxD) is connected to the internal
receiver data logic, and the transmit shift clock pin
(TxC)isconnected totheinternal receivershiftclock
logic.All other features of theSIO are unaffected.
BAUD RATE GENERATORS
Each channel in the SIO contains a programmable
baud rate generator (BRG). Each BRG consists of
an 8-bittimeconstant register, an 8-bit down coun-
ter, a control register, and a flip-flop ontheoutput to
provide a square wave signalout. In addition tothe
flip-flop on the output, there is also a flip-flop on the
inputclock;therefore, themaximum outputfrequen-
cy oftheBRGisone-forth oftheinput clockfrequen-
cy. This maximum output frequency occurs when
divide by four mode is selected, and the time
constant register is loaded with the minimum count
of ”01H”. The equation to determine the output fre-
quencyis :
Output
=
Frequency
(divide by selected) X (time constant
value indecimal)
Input Frequency
Figure 7
: Interrupt Structure.
V000380
MK68564
12/46
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相關代理商/技術參數(shù) |
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| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
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| MK68564Q-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68590P | 制造商:STMicroelectronics 功能描述: |
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