參數(shù)資料
型號(hào)： MK68564
廠商： 意法半導(dǎo)體
英文描述： Serial Input Output(串行I/O(雙通道,多功能外圍電路))
中文描述： 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路））
文件頁(yè)數(shù)： 16/46頁(yè)
文件大?。?/td> 464K
代理商： MK68564
Command 2 has been issued, and another Exter-
nal/Status interrupt request will be generated. This
interrupt should also be handled
Command 2 to reinitialize the external/status logic.
At theendof the break sequence, asinglenull char-
acterwill be left in the receive data FIFO.This char-
acter should be read and discarded.
Because Parity Error and Receive Overrun Error
flags are latched, the error status that is read from
Status Register 1 reflects an error in the current
word in the receive data FIFO, plus anyparityor o-
verrun errors received since the last Error Reset
command. To keep correspondence between the
state of the error FIFO and the contents of the re-
ceive data FIFO, Status Register 1 should be read
before the receive buffer. If the status is read after
the data and more than one character is stackedin
the data FIFO during the read of the receive buffer,
the status flagsread will be for the next word. Keep
inmindthat whena character is shiftedupto the top
of the data FIFO (the receive buffer), its error flags
are shifted into StatusRegister 1
.Anexception to the normal flow of data through the
receive data FIFO occurs when the Receive Inter-
rupt On First Character Only mode is selected. A
Special Receive Condition interrupt in this mode
holds the error data, and the character itself (even
if read from the data FIFO) until the Error Reset
command (command6)isissued. Thisprevents fur-
ther data from becoming available in the receiver,
until Command 6 is issued, and allows CPU inter-
vention on the character with the error even if DMA
or block transfer techniques are being used.
by issuing
SYNCHRONOUS OPERATION
INTRODUCTION
Before
transmission and reception, the three typesof char-
actersynchronization - Monosync, Bysync, and Ex-
ternal Sync - require some explanation. These
modes use the x1 clock for both Transmit and Re-
ceiveoperations. Dataissampledonthe risingedge
of the Receive Clock input (RxC). Transmitter data
transitions occur on the falling edge of the Transmit
Clock input (TxC).
The differences between Monosync, Bisync, and
External Sync are in the manner in which initial re-
ceive character synchronization is achieved. The
mode of operation must be selected before sync
characters are loaded, because theregisters are u-
sed differently in the various modes. Figure 10
showstheformats forallthreesynchronous modes.
MONOSYNC. In the Monosync mode (8-bit sync
describing
byte-oriented,
synchronous
mode), the transmitter transmits the sync character
inSyncWordRegister 1.Thereceivercomparesthe
single sync character with the programmed sync
character stored in Sync Word Register 2. A match
implies character synchronization and enables data
transfer. The SYNCpin is used as an output in this
mode and is active for the part of the receive clock
that detects the sync character.
BISYNC.IntheBisync mode(16-bit syncmode),the
transmitter transmits the sync character in Sync
Word Register 1 followed by the sync character in
Sync Word Register 2. The receiver compares the
two contiguous sync characters with the program-
medsynccharactersstored inSync WordRegisters
1 and 2. Amatch implies character synchronization
and enables data transfer. TheSYNCpin isused as
an output in this mode and is active for the part of
the receive clock that detects the sync characters.
External Sync
. In the External Sync mode, the
transmitter transmits the sync character in Sync
Word Register 1. Character synchronization for the
receiver is established externally. The SYNC pin is
an input that indicates that external character syn-
chronization has been achieved. After the syncpat-
tern is detected, the external logic must wait for two
fullReceive Clockcycles toactivate the SYNC input
pin(seefigure 11).TheSYNCinput pinmustbeheld
Low until character synchronization is lost. Charac-
ter assembly begins on the rising edge of the Re-
ceive Clock that precedes the falling edge of the
SYNC input pin.
In all cases, afterareset (hardware or software), the
receiver is in theHunt phase, during which timethe
SIO looks for character synchronization. The Hunt
phasecan begin only when the receiver is enabled,
and data transfer can begin only when character
synchronization has been achieved. If character
synchronization islost,theHuntphase canbere-en-
tered by setting the Enter Hunt Mode bit in the Re-
ceiver Control Register. In the transmit mode, the
transmitter always sends the programmed number
of syncbits (8 or 16), regardless of the bits perchar-
acter programmed.
IntheMonosync, Bisync,and ExternalSync modes,
assemblyof received datacontinues until theSIO is
reset, or untilthe receiver is disabled (by command
ortheDCDpin intheRxAuto Enables mode),orun-
til the CPU sets the Enter Hunt Mode bit.
After initial synchronization has been achieved, the
operation of the Monosync, Bisync, and External
Sync modes is quite similar. Any differences are
specified in thefollowing text.
To set up the SIO for Synchronous operations, the
following registers need to be initialized : Mode
MK68564
16/46
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