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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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Bisync ProtocolTransmission
. InaBisync Proto-
col operation, once synchronization isachieved be-
tween the transmitter and receiver, fill characters
are inserted to maintain that synchronization when
the transmitter has nomore datato send. The diffe-
rentoptionsavailable intheSIOaredescribedin the
TransmitUnderrun/End OfMessagepartofthissec-
tion.If pad characters areto be sentinplaceof sync
characters following the transmission of the CRC,
the program canset the SIO transmitter toeight bits
per character and then load ”FFH” to the transmit
buffer while the CRC characters are being sent. Al-
ternatively, thesynccharacters in SyncWordRegis-
ters 1 and 2 can be redefined to bepad characters
during this time. The following example is included
to clarify this point :
TheSIOinterrupts theCPUwithaTransmit Interrupt
when the Tx Buffer Empty bit is set.
TheCPUrecognizes thatthelast character (ETX)of
the message has already been sent to the SIO
transmit buffer by examining the internal program
status.
To force the SIO to send CRC,the CPU issues the
Reset Tx Underrun/EOM Latch command and
clears thecurrent Transmit Interrupt with the Reset
Tx Interrupt Pending command. Resetting the inter-
rupt with this command prevents the SIO from re-
questing more data. The SIO then begins to send
CRC (because the transmitter is in an underrun
condition) and sets the Transmit Underrun/EOM
Latch, which causes an External/Status Interrupt.
The CPU satisfies the External/Status Interrupt by
loading pad characters into the transmit buffer and
clears the interrupt by issuing the Reset Exter-
nal/Status Interrupt command.
The pad character will follow the CRC characters in
thissequence, instead of theusualsynccharacters.
A Transmit Interrupt is generated when the pad
character is loaded into the transmit shift register.
From this point on, the CPU can send more pad
characters or sync characters.
The transparent mode of operation in Bisync Proto-
col ismade possible with theSIO’sability to change
the Tx CRC Enable bit at any time during program
sequencing and with the additional capability of in-
serting 16-bit sync characters. Exclusion of DLE
(Data Link Escape) characters from CRC calcula-
tion can be achieved by disabling CRC calculations
immediately preceding the DLE character transfer
to the transmit buffer. In the case of a transmit un-
derrun condition in the transparent mode, a pair of
DLE-SYN characters is sent. The SIO can be pro-
grammed to send theDLE-SYNC sequence by loa-
dingaDLEcharacter intoSyncWordRegister 1and
a SYNC character into Sync Word Register 2.
The SIO always transmits two sync characters (16
bits) in Bisync mode. If additional sync characters
are to be transmitted before a message, the CPU
candelayloading data tothetransmit bufferuntilthe
required number of syncshave been sent. No CRC
calculations are done onany automatically inserted
sync characters. An alternate method of sending
additional sync characters is to load the sync char-
acters into the transmit buffer, in which case the
transmitter willtreat the characters as data. The Tx
CRC Enablebit should not be set, untiltrue data is
going to be loaded into the buffer, to avoid perfor-
ming CRC calculations on the additional sync char-
acters.
SYNCHRONOUSRECEIVE
Initialization
. Byte-oriented receive programs are
usually initialized with the following parameters :
odd-evenornoparity,x1clockmode(necessarybe-
cause of the start bit detection logic), 8- or 16-bit
sync character(s), CRC polynomial, Receiver En-
ables, interrupt modes, and receive character
length. Care must be taken if Parity is enabled. The
receiver will usually detect a Parity Error on all sync
characters, after synchronization is achieved, and
on the CRCcharacters.
Receiver Hunt Mode
. Afterthe SIO is initialized for
a Synchronous receive operation, the receiver is in
theHuntphase. During theHunt phase, thereceiver
does a bit-by-bit comparison of the incoming data
stream andthe synccharacter(s) stored intheSync
Word Register 2 (for Monosync mode) and Sync
Word Registers 1 and 2 (for Bisync mode). When a
matchoccurs, theHunt phaseisterminated, and the
following databits are assembled into the program-
med character length and loaded into the receive
data FIFO.
ReceiveCharacteristics
. The receivermay bepro-
grammed to assemble five to eight data bits into a
character. The character is right-justified inthe shift
register andtransferred tothereceive data FIFO. All
data transfers to theFIFOare in8-bit groups. When
the programmed character length is less than eight
bits, the most significant bit(s) transferred with a
characterwillbetheleast significant bit(s)ofthe next
character. The programmed character length may
be changed on the fly during a message ; however,
caremust be taken to assure that the change is ef-
fective before the number of bits specified for the
character length have been assembled.
Whenthe Sync Character Load Inhibit bit inthe Re-
ceiver Control Register is set, all characters in the
MK68564
20/46
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相關(guān)代理商/技術(shù)參數(shù) |
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| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
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