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參數(shù)資料
| 型號(hào)： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 6/64頁 |
| 文件大?。?/td> | 429K |
| 代理商： | MK50H28Q25/XX |
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STATUS ENQUIRY
is received, the device is-
sues
the
LMI Received
primitive 13
(with
PPARM=1) and expects the host to respond with
LMI Status Request Primitive 11 with UPARM=0
(when the host is ready to transmit the Full
STATUS frame).
Asynchronous STATUS frames may be transmit-
ted by placing the data to be transmitted into the
appropriate buffer and issueing Primtive 11 with
UPARM=2.
LMI frames received in any mode will not cause
Receive Interrupts (RINT) to be generated, nor
will the Receive Interrupt Ring be updated. In-
stead, the MK50H28 will issue primitives corre-
sponding to those LMI Frame received which are
not automatically processed by the MK50H28 (i.e.
non ”LIV only” frames). See the description of
primitives in section 4.1.2.2.
In addition to the
primitives, bits 09-11 of the Receive Message De-
scriptor 0 (RMD0) for the LMI channel will indicate
the type of frame received. See section 4.3.1.2
for details.
In Non-Auto-LMI mode of operation, LMI frames
received on the LMI Channel (typically DLCI 0)
will be written into the receive buffer as Transpar-
ent or SVC frames.
Also refer to Detailed Programming Procedures
(section 4.4) for more information on using the
device in the previously mentioned modes of Pro-
tocol Operation.
MK50H28
14/64
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