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參數(shù)資料
| 型號： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 33/64頁 |
| 文件大小： | 429K |
| 代理商： | MK50H28Q25/XX |
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BIT
NAME
DESCRIPTION
15
OWNA
When this bit is a zero the HOST owns this descriptor. When this bit is a one the
MK50H28 owns this descriptor. The chip clears the OWNA bit after filling the buffer
pointed to by the descriptor entry provided a valid frame has been received. The Host
sets the OWNA bit after emptying the buffer. Once the MK50H28 or the Host has
relinquished ownership of a buffer, it may not change any field in the four words that
comprise the descriptor entry.
14
EOR
End Of Ring. This bit is set by the host to indicate that this is the last descriptor in the
ring.
13
C/R
Command/Response Indication Bit. This bit equals the state of the C/R bit for the
received frame.
12
ELF
End of Long Frame indicates that this is the last buffer used by the MK50H28 for this
frame. ELF is used for data chaining buffers and is set by the MK50H28. ELF=0
indicates that this buffer is one in a chain. When not chaining, ELF will always be one.
11
FECN
Forward Explicit Congestion Notification Bit. This bit equals the state of the FECN bit for
the received frame.
10
BECN
Backward Explicit Congestion Notification Bit. This bit equals the state of the BECN bit for
the received frame.
09
DE
Discard Eligibility Bit. This bit equals the state of the DE bit for the received frame.
08
FRER
Frame in Error Bit. This bit is valid only if RBFRS is set in CTADR+12. This bit will be set
by the MK50H28 only if an aborted or a bad FCS frame is received.
07:00
RBADR
The High Order 8 address bits of the buffer pointed to by this descriptor. This field is
written by the Host and unchanged by MK50H28.
4.3.1 Receive Message Descriptor Entry
4.3.1.1 Receive Message Descriptor 0 (RMD0) For Non-LMI Channel
1
5
1
4
1
3
0
7
0
8
1
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
RBADR<23:16>
O
W
N
A
E
O
R
E
L
F
C/R
E
F
C
N
E
B
C
N
DE
R
F
E
R
4.3.1.2 Receive Message Descriptor 0 (RMD0) For LMI Channel
1
5
1
4
1
3
0
7
0
8
1
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
RBADR<23:16>
O
W
N
A
E
O
R
E
L
F
0
R
F
E
R
Frame
Type
BIT
NAME
DESCRIPTION
15
OWNA
When this bit is a zero, the HOST owns this descriptor. When this bit is a one the
MK50H28 owns this descriptor. The chip clears the OWNA bit after filling the buffer
pointed to by the descriptor entry, provided a valid frame has been received. The Host
should set the OWNA bit after emptying the buffer. Once the MK50H28 or Host
relinquishes ownership of a buffer, it may not change any field in the descriptor entry.
MK50H28
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