- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98023 > MK50H28Q25/XX (STMICROELECTRONICS) 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 PDF資料下載
參數(shù)資料
| 型號： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 42/64頁 |
| 文件大?。?/td> | 429K |
| 代理商： | MK50H28Q25/XX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當(dāng)前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
4.4.2.3 Bi-directional Procedures (Auto LMI Mode) - Continued
3. After every nN1/N391 transmissions of STATUS ENQUIRY with Report Type of ”LIV Only”, the
MK50H28 transmits a STATUS ENQUIRY with Report Type of ”Full Status”.
4. A received Full STATUS frame will be stored into the LMI channel buffer, the sequence number
checking will be performed, and its reception will be indicated to the host via Provider Primitive
13. A received Asynchronous STATUS frame will be stored into the LMI channel buffer and its
reception will be indicated to the host via Provider Primitive 14.
5. The MK50H28 also automatically responds to a STATUS ENQUIRY (”LIV Only”) frame received
by transmitting a STATUS (”LIV Only”) frame along with restarting the nT2 timer. When a ”Full
Status” STATUS ENQUIRY is received, the device issues the LMI Received primitive 13 (with
PPARM=1) and expects the host to respond with LMI Status Request Primitive 11 with
UPARM=0 (when ready to transmit the Full STATUS frame).
6. Asynchronous STATUS frames may be transmitted by placing the data to be transmitted into the
appropriate buffer and issueing Primtive 11 with UPARM=2.
4.4.3 Sending Data On A Link
Use the following procedure to send a frame:
1. Make sure that ACTIVE bit in the ALT and TXRDY bit in the CT are set for that channel.
2. Make sure that the Transmit Ring Pointer, Current Transmit Descriptor and address field infor-
mation in the CT is valid.
3. Wait for the OWNA bit of the current transmit descriptor to be cleared, if it is not already.
4. Fill the buffer associated with the current transmit descriptor with the data to be sent, or set the
descriptor buffer address to any already filled buffer.
5. Repeat steps 3 & 4 for next buffer if chaining is necessary, setting ELF & MCNT appropriately.
6. Set the OWNA bit for each descriptor to be used in sending the frame.
7. Go on to next descriptor. The MK50H28 will clear OWNA bits when the frame has been transmitted.
4.4.4 Receiving Data On A Link
The following procedure should be followed when receiving a frame:
1. Make sure that ACTIVE bit in the ALT and RXRDY bit in the CT are set for that channel.
2. Make sure that the Index to CT in the ALT points to appropriate CT entry for that channel.
3. Also make sure that the Receive Ring Pointer, Current Receive Descriptor information in the CT
is valid.
4. Make sure the OWNA bit of the current receive descriptor is clear.
5. A Receive Interrupt (RINT) will indicate reception of a frame.
6. Read the entry or entries in the Receive Interrupt Descriptor Ring that have the SRVC bit set.
The Receive Context Table Address and Current Receive Descriptor index available here indi-
cate the CT entry and the descriptor within the Rx Ring associated with the received frame.
6. Read data out of the buffer associated with the current receive descriptor.
8. Set the OWNA bit of the current receive descriptor to return ownership to the MK50H28.
9. If the ELF bit of the current receive descriptor is clear, then go on to the next descriptor and re-
peat from step 4 appending data from each buffer until a descriptor with ELF=1 is reached.
10. LMI frames received in any mode will not cause Receive Interrupts (RINT) to be generated, nor
will the Receive Interrupt Ring be updated. Instead, the MK50H28 will issue primitives corre-
sponding to the received LMI Frames which are not automatically processed by the MK50H28
(i.e. non ”LIV only” frames). See the description of primitives in section 4.1.2.2.
11. For frames received on the LMI Channel (typically DLCI 0), bits 09-11 of the Receive Message
Descriptor 0 (RMD0) for the LMI channel will indicate the type of frame received. A setting of
000 indicates a received SVC frame or Transparent Mode frame. See section 4.3.1.2 for details.
MK50H28
47/64
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK50N512CLL100R | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100 |
| MK50X256CLL100 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100 |
| MK50N512CLL100 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100 |
| ML53812-2 | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP176 |
| ML54051 | FLASH MEMORY DRIVE CONTROLLER, PQFP120 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK50H28TQ25 | 功能描述:電信集成電路 MLL Controller 25MHz RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| MK50N512CLL100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
| MK50N512CLQ100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
| MK50N512CMC100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
| MK50N512CMD100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。