- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98023 > MK50H28Q25/XX (STMICROELECTRONICS) 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 PDF資料下載
參數(shù)資料
| 型號(hào)： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 429K |
| 代理商： | MK50H28Q25/XX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
4.2.1 Mode Register
The Mode Register allows alteration of the MK50H28’s operating parameters.
1
5
1
4
1
3
0
7
0
8
1
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
LBACK
<2:0>
MFS
<4:0>
IADR + 00
C
S
F
D
R
F
C
S
D
T
F
C
S
0000
0
BIT
NAME
DESCRIPTION
15:11
MFS<4:0>
Minimum Frame Spacing defines the minimum number of flag sequences transmitted
between adjacent frames transmitted by the MK50H28. This only affects frames
transmitted by the MK50H28 and does not restrict the spacing of the
frames received by the MK50H28.
When using RTS/CTS control this field defines
the number of flags transmitted at the beginning of the frame after CTS is driven
low (minus one for the trailing flag). See the following table for encoding of this field.
10:06
0
Reserved. Must be written as zeros.
05
DRFCS
Disable Receiver FCS (CRC). When DRFCS = 0, the receiver will extract and check the
FCS field at the end of each frame. When DRFCS = 1, the receiver continues to extract
the last 16 or 32 bits of each frame, depending on FCSS, but no check is performed to
determine whether the FCS is correct. If the received frame is an even number of
bytes, the first 16 bits of the FCS will be appended to the end (as indicated by MCNT) of
the receive buffer data.
04
DTFCS
Disable Transmitter FCS. When DTFCS=0, the transmitter will generate and append the
FCS to each signal unit. When DTFCS = 1, the FCS logic is disabled, and no FCS is
generated with transmitted frames. Setting DTFCS = 1 is useful in loopback testing for
checking the ability of the receiver to detect an incorrect FCS.
03
FCSS
FCS Select. When FCSS = 1, a 16-bit FCS is selected otherwise a 32-bit FCS is used.
NUMBER OF FLAGS
MFS<4:0>
NUMBER OF FLAGS
MFS<4:0>
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
0
2
4
9
18
5
11
22
12
25
19
7
15
31
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
28
24
17
3
6
13
27
23
14
29
26
21
10
20
8
16
MK50H28
28/64
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK50N512CLL100R | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100 |
| MK50X256CLL100 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100 |
| MK50N512CLL100 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100 |
| ML53812-2 | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP176 |
| ML54051 | FLASH MEMORY DRIVE CONTROLLER, PQFP120 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK50H28TQ25 | 功能描述:電信集成電路 MLL Controller 25MHz RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| MK50N512CLL100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
| MK50N512CLQ100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
| MK50N512CMC100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
| MK50N512CMD100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。