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參數資料
| 型號： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 37/64頁 |
| 文件大?。?/td> | 429K |
| 代理商： | MK50H28Q25/XX |
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BIT
NAME
DESCRIPTION
15
OWNA
When this bit is a zero, the HOST owns this descriptor. When this bit is a one the
MK50H28 owns this descriptor. The host sets the OWNA bit after filling the buffer
pointed to by the descriptor entry. The MK50H28 releases the descriptor after
transmitting the buffer. After the MK50H28 or the Host has relinquished ownership of a
buffer, it may not change any field in the four words that comprise the descriptor entry.
14
EOR
End Of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring.
13
C/R
Command/Response Indication Bit. This bit determines the state of the C/R bit for the
transmitted frame.
12
ELF
End of Long Frame indicates that this is the last buffer used by the MK50H28 for this
frame. It is used for data chaining buffers. ELF is set by the Host. When not chaining,
ELF should be set to a one.
11
FECN
Forward Explicit Congestion Notification Bit. This bit determines the state of the FECN bit
for the transmitted frame.
10
BECN
Backward Explicit Congestion Notification Bit. This bit determines the state of the BECN
bit for the transmitted frame.
09
DE
Discard Eligibility Bit. This bit determines the state of the DE bit for the transmitted frame.
If in the CT entry TXCONG=1, any frame with DE=1 will not be transmitted, but discarded.
08
TINTD
Transmit Interrupt Disable. If this bit is set, no transmit interrupt is generated when
ownership of this descriptor is released back to the host.
07:00
TBADR
The High Order 8 address bits of the buffer pointed to by this descriptor.
This field is written by the Host and unchanged by MK50H28.
4.3.2.2 Transmit Message Descriptor 0 (TMD0) For LMI Channel
1
5
1
0
1
4
0
9
1
2
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
1
3
TBADR<23:16>
O
W
N
A
E
O
R
E
L
F
T
I
N
T
D
0
Frame
Type
BIT
NAME
DESCRIPTION
15
OWNA
When this bit is a zero, the HOST owns this descriptor. When this bit is a one the
MK50H28 owns this descriptor. The host sets the OWNA bit after filling the buffer pointed
to by the descriptor entry. The MK50H28 releases the descriptor after transmitting the
buffer. After the MK50H28 or the Host has relinquished ownership of a buffer, it may not
change any field in the four words that comprise the descriptor entry.
14
EOR
End of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring.
13
0
Reserved. Must be written as zero
12
ELF
End of Long Frame indicates that this is the last buffer used by the MK50H28 for this
frame. It is used for data chaining buffers. ELF is set by the Host. When not chaining,
ELF should be set to a one.
MK50H28
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