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參數(shù)資料
| 型號： | MK50H28Q25/XX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 429K |
| 代理商： | MK50H28Q25/XX |
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4.2.7 Status Buffer Address
1
5
1
4
1
3
0
7
0
8
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
IADR + 40
IADR + 42
SBA<15:00>
SBA<23:16>
0
nN1
(If EIBEN = 1)
BIT
NAME
DESCRIPTION
15:08
0
Must be written as zeroe if CSR2<14> bit EIBEN = 0
07:00/15:00
SBA
STATUS BUFFER ADDRESS points to a 9 word status buffer into which status
information is placed upon the issuance of the Status Request primitive by the HOST.
The status buffer must begin on a word boundary.
4.2.8 Error Counters Twenty two words in the Initialization Block are reserved for use as error count-
ers and statistics which the MK50H28 will increment as required. These counters are intended for use by
the host CPU for statistical analysis on the LMI channel. The Error Counters at IADR+44, 46,48,64, and
66 are applicable to all the active channels (i.e., both LMI and non-LMI). If RBFRS bit (in Context Table
CTADR+12, bit 09) = 0, bad frames are ignored by the MK50H28. However, if RBFRS = 1 even the bad
frames will be received by the MK50H28. For such received bad frames the FRER bit will be set in the
Receive Message Descriptor 0. The MK50H28 will only increment the Error Counters; it is up to the user
to clear, reset, or preset them (Stop or Re-initialization will not reset them). The error counters are:
Memory Address
Error Counter
IADR+44
Bad Frames Received (Bad FCS or Non-Octet Aligned)
IADR+46
Short Frames (less than: 2 bytes non-LMI, 3 bytes Annex A/D, 4 bytes other LMI frame)
IADR+48
Aborted Frames received
IADR+50
LIV/LMI Frames with missing or incorrect Report Type IE received. (The appropriate
corresponding IE Identifiers were not received). (Annex A)
IADR+52
LIV/LMI Frames with incorrect Report Type format Received. (Annex A or Annex D)
IADR+54
LIV/LMI Frames with incorrect Report Type format Received. (Annex A)
IADR+56
Number of nT1/T391 timeouts for LIV/LMI frames. This error counter is only
incremented when nT1 expires without having received a STATUS frame.
IADR+58
Number of nT2/T392 timeouts for LIV/LMI frames. This error counter is only
incremented when nT2 expires without having received a STATUS ENQUIRY frame.
IADR+60
Frames received with bad sequence errors.
IADR+62
Number of Annex D frames received with bad format.
IADR+64
Number of good frames received on unknown or inactive DLCIs.
IADR+66
Number of received frames exceeding the maximum frame length dN1.
IADR+68
LIV Status Enquiry Messages Received
IADR+70
LIV Status Messages Received
IADR+72
LIV Full Status Enquiry Messages Received
IADR+74
LIV Full Status Messages Received
IADR+76
Asynchronous Messages Received
IADR+78
LIV Status Enquiry Messages Transmitted
IADR+80
LIV Status Messages Transmitted
IADR+82
LIV Full Status Enquiry Messages Transmitted
IADR+84
LIV Full Status Messages Transmitted
MK50H28
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