參數(shù)資料
型號: MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 66/98頁
文件大?。?/td> 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
66 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.4.10
TestDAC1Reg register
Defines the test value for TestDAC1.
Table 136. TestDAC1Reg register (address 39h); reset value: xxh bit allocation
Bit
7
6
5
Symbol
reserved
Access
-
Table 137. TestDAC1Reg register bit descriptions
Bit
Symbol
7
reserved
6
reserved
5 to 0
TestDAC1[5:0] defines the test value for TestDAC1. Output of DAC1 can be routed to
AUX1 by setting value AnalogSelAux1[3:0] to 0001b in the
AnalogTestReg register
9.2.4.11
TestDAC2Reg register
Defines the test value for TestDAC2.
Table 138. TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation
Bit
7
6
5
Symbol
reserved
Access
-
Table 139. TestDAC2Reg register bit descriptions
Bit
Symbol
7 to 6
reserved
5 to 0
TestDAC2[5:0] defines the test value for TestDAC2. DAC2 output can be routed to
AUX2 by setting value AnalogSelAux2[3:0] to 0001b in the
AnalogTestReg register
9.2.4.12
TestADCReg register
Shows the values of ADC I-channel and Q-channel.
Table 140. TestADCReg register (address 3Bh); reset value: xxh bit allocation
Bit
7
6
5
Symbol
ADC_I[3:0]
Access
R
Table 141. TestADCReg register bit descriptions
Bit
Symbol
7 to 4
ADC_I[3:0]
3 to 0
ADC_Q[3:0]
4
3
2
1
0
TestDAC1[5:0]
R/W
Description
reserved for production tests
reserved for future use
4
3
2
1
0
TestDAC2[5:0]
R/W
Description
reserved for future use
4
3
2
ADC_Q[3:0]
R
1
0
Description
ADC I-channel value
ADC Q-channel value
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