參數(shù)資料
型號: MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 21/98頁
文件大小: 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
21 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
8.3.4.8
High-speed mode
In High-speed mode (HS mode), the device can transfer information at data rates of up to
3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard modes
(F/S modes) for bidirectional communication in a mixed-speed bus system.
8.3.4.9
High-speed transfer
To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to
I
2
C-bus operation.
The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger
on the SDA and SCL inputs and different timing constants when compared to
F/S mode
The output buffers of the device in HS mode incorporate slope control of the falling
edges of the SDA and SCL signals with different fall times compared to F/S mode
8.3.4.10
Serial data transfer format in HS mode
The HS mode serial data transfer format meets the Standard mode I
2
C-bus specification.
HS mode can only start after all of the following conditions (all of which are in F/S mode):
1. START condition (S)
2. 8-bit master code (00001 XXXb)
3. Not-acknowledge bit (A)
When HS mode starts, the active master sends a repeated START condition (Sr) followed
by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from
the selected MFRC523.
Data transfer continues in HS mode after the next repeated START (Sr), only switching
back to F/S mode after a STOP condition (P). To reduce the overhead of the master code,
a master links a number of HS mode transfers, separated by repeated START conditions
(Sr).
Fig 18. I
2
C-bus HS mode protocol switch
F/S mode
HS mode (current-source for SCL HIGH enabled)
F/S mode
001aak749
A
A
A/A
DATA
(n-bytes + A)
S
R/W
MASTER CODE
Sr SLAVE ADDRESS
HS mode continues
Sr
SLAVE ADDRESS
P
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