參數(shù)資料
型號(hào)： MFRC52301HN1
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Contactless reader IC
封裝： MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù)： 63/98頁
文件大?。?/td> 1666K
代理商： MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
63 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.4.5
TestPinValueReg register
Defines the high and low values for the test port D1 to D7 when it is used as I/O.
Table 126. TestPinValueReg register (address 34h); reset value: 00h bit allocation
Bit
7
6
5
Symbol
UseIO
Access
R/W
Table 127. TestPinValueReg register bit descriptions
Bit
Symbol
Value Description
7
UseIO
1
9.2.4.6
TestBusReg register
Shows the status of the internal test bus.
Table 128. TestBusReg register (address 35h); reset value: xxh bit allocation
Bit
7
6
5
Symbol
Access
Table 129. TestBusReg register bit descriptions
Bit
Symbol
7 to 0
TestBus[7:0]
9.2.4.7
AutoTestReg register
Controls the digital self-test.
Table 130. AutoTestReg register (address 36h); reset value: 40h bit allocation
Bit
7
6
5
Symbol
reserved
AmpRcv
reserved
4
3
2
1
0
TestPinValue[5:0]
R/W
reserved
-
enables the I/O functionality for the test port when one of the
serial interfaces is used. The input/output behavior is defined
by value TestPinEn[5:0] in the TestPinEnReg register
defines the value of the test port when it is used as I/O and
each output must be enabled by TestPinEn[5:0] in the
TestPinEnReg register
Remark:
Reading the register indicates the status of pins D6
to D1 if the UseIO bit is set to logic 1. If the UseIO bit is set to
logic 0, the value of the TestPinValueReg register is read back.
reserved for future use
6 to 1 TestPinValue[5:0]
-
0
reserved
-
4
TestBus[7:0]
R
3
2
1
0
Description
shows the status of the internal test bus. The test bus is selected using
the TestSel2Reg register; see
Section 16.1 on page 80
4
3
2
SelfTest[3:0]
1
0
EOFSOF
Adjust
R/W
Access
-
R/W
-
R/W
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