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| 型號： | MFRC52301HN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Contactless reader IC |
| 封裝： | MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html& |
| 文件頁數(shù)： | 48/98頁 |
| 文件大小： | 1666K |
| 代理商： | MFRC52301HN1 |
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MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
48 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.2.5
TxControlReg register
Controls the logical behavior of the antenna driver pins TX1 and TX2.
Table 62.
Bit
Symbol
Table 63.
Bit Symbol
7
InvTx2RFOn 1
6
InvTx1RFOn 1
5
InvTx2RFOff 1
4
InvTx1RFOff 1
6 to 4
RxSpeed[2:0]
defines the bit rate while receiving data. The MFRC523
manages transfer speeds up to 848 kBd
106 kBd
212 kBd
424 kBd
848 kBd
reserved
reserved
reserved
reserved
an invalid received data stream (less than 4 bits received) will
be ignored and the receiver remains active
receiver is deactivated after receiving a data frame
able to receive more than one data frame
only valid for data rates above 106 kBd in order to handle the
polling command
after setting this bit, the Receive and Transceive commands will
not terminate automatically. Multiple reception can only be
deactivated by writing any command (except the Receive
command) to the CommandReg register, or by the host clearing
the bit
if set to logic 1, an error byte is added to the FIFO buffer at the
end of a received data stream which is a copy of the ErrorReg
register value
defines the expected framing for data reception
ISO/IEC 14443 A/MIFARE
reserved
reserved
ISO/IEC 14443 B
000
001
010
011
100
101
110
111
1
3
RxNoErr
2
RxMultiple
0
1
1 to 0
RxFraming
00
01
10
11
Table 61.
Bit
RxModeReg register bit descriptions
…continued
Symbol
Value
Description
TxControlReg register (address 14h); reset value: 80h bit allocation
7
6
5
InvTx2RF
On
On
Off
R/W
R/W
R/W
4
3
2
1
0
InvTx1RF
InvTx2RF
InvTx1RF
Off
R/W
Tx2CW reserved Tx2RFEn
Tx1RFEn
Access
R/W
-
R/W
R/W
TxControlReg register bit descriptions
Value Description
output signal on pin TX2 inverted when driver TX2 is enabled
output signal on pin TX1 inverted when driver TX1 is enabled
output signal on pin TX2 inverted when driver TX2 is disabled
output signal on pin TX1 inverted when driver TX1 is disabled
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