參數(shù)資料
型號: MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 38/98頁
文件大?。?/td> 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
38 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.1.5
ComIrqReg register
Interrupt request bits.
Table 30.
Bit
Symbol
Access
Table 31.
All bits in the ComIrqReg register are cleared by software.
Bit Symbol
Value Description
7
Set1
1
indicates that the marked bits in the ComIrqReg register are set
0
indicates that the marked bits in the ComIrqReg register are cleared
6
TxIRq
1
set immediately after the last bit of the transmitted data was sent out
5
RxIRq
1
receiver has detected the end of a valid data stream
if the RxModeReg register’s RxNoErr bit is set to logic 1, the RxIRq bit is
only set to logic 1 when data bytes are available in the FIFO
4
IdleIRq
1
if a command terminates, for example, when the CommandReg changes
its value from any command to the Idle command (see
Table 150 on
page 68
)
if an unknown command is started, the CommandReg register
Command[3:0] value changes to the idle state and the IdleIRq bit is set
the microcontroller starting the Idle command does not set the IdleIRq bit
3
HiAlertIRq
1
the Status1Reg register’s HiAlert bit is set
the HiAlertIRq bit stores this event and can only be reset as indicated by
the Set1 bit in this register
2
LoAlertIRq
1
Status1Reg register’s LoAlert bit is set
the LoAlertIRq bit stores this event and can only be reset as indicated by
the Set1 bit in this register
1
ErrIRq
1
any error bit in the ErrorReg register is set
0
TimerIRq
1
the timer decrements the timer value in register TCounterValReg to zero
ComIrqReg register (address 04h); reset value: 14h bit allocation
7
6
5
4
Set1
TxIRq
RxIRq
IdleIRq
W
D
D
D
3
2
1
0
HiAlertIRq
D
LoAlertIRq
D
ErrIRq
D
TimerIRq
D
ComIrqReg register bit descriptions
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