參數(shù)資料
型號(hào): MDS212CG
廠(chǎng)商: ZARLINK SEMICONDUCTOR INC
元件分類(lèi): 網(wǎng)絡(luò)接口
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA456
封裝: 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456
文件頁(yè)數(shù): 95/111頁(yè)
文件大小: 1609K
代理商: MDS212CG
MDS212
Data Sheet
95
Zarlink Semiconductor Inc.
18.2.11.10 CPUIRRDY - Internal Ram Read Ready For CPU
Access:
Address:
The Frame Engine sets this ready bit to notify the CPU that the requested data is ready to read.
Non-Zero-Wait-State,
h594
Direct Access,
Write/Read
Bit [0]
Bit [31:1]
R_RDY
Reserved
Data in Data registers is ready for CPU Read
18.2.11.11 LEDR - LED Register
Access:
Address:
Non-Zero-Wait-State,
h598
Direct Access,
Write/Read
Bit [7:0]
Bit [15:8]
Bit [23:16]
Bit [25:24]
UDEF1
UDEF2
UDEF3
HT
User defined information status 1 for debug purpose
User defined information status 2 for debug purpose
User defined information status 3 for debug purpose
Holding time for LED signal (Default=00)
00=8msec
01=16msec
10=32msec
11-64msec
LED Clock frequency (Default=00)
00=100M/8=12.5Mhz
01=100M/16=6.25Mhz
10=100M/32=3.125Mhz11=100M/64=1.5625Mhz
Bit [27:26
LCLK]
Bit [30:28]
Bit [31]
Reserve
SS
Start Shift out the status bits out from the master device. This bit
has no effect on slave chip.
Note:
UDEF1-UDEF3 are used for debug purpose. The contents of UDEF1-3 are loaded by CPU and the usage of
these are up to software.
18.2.12 Ethernet MAC Port Control Registers
One set for each Ethernet MAC Port [11:0]
18.2.12.1 ECR0 - MAC Port Control Register
Access:
Address:
Non-Zero-Wait-State,
h0x0*4
ECR0_p0
ECR0_p1
ECR0_p2
ECR0_p3
ECR0_p4
ECR0_p5
ECR0_p6
Direct Access,
x: port n (n=0 - 11)
Write/Read
h000
h040
h080
h0c0
h100
h140
h180
31
1
0
RDY
31
30
28
27
26
25
24
23
16
15
8
7
0
SS
LCK
HT
UDEF3
UDEF2
UDEF1
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