參數(shù)資料
型號(hào): MDS212CG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA456
封裝: 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456
文件頁(yè)數(shù): 77/111頁(yè)
文件大小: 1609K
代理商: MDS212CG
MDS212
Data Sheet
77
Zarlink Semiconductor Inc.
18.2.4.3 BCT - (FCB) Buffer Counter Threshold
Access
Address:
Non-Zero-Wait-State
h74C
Direct-Access
Write/Read
Bit[9:0]
Low_Limit
Low limit number of frames to each destination port (i.e., Source
port limits the # of FCB used by each destination port)
High limit number of frames to each destination port (i.e.,
Source port limits the # of FCB used by each destination port)
Bit[19:10
HI_Limit
18.2.4.4 BCHL - Buffer Counter Hi-low Selection
Access
Address:
Non-Zero-Wait-State
h750
Direct-Access
Write/Read
Bit[11:0]
Lp_Hi_Low Sel
Selection for Low or High Limit of Buffer Counter for Local
device 12 bits maps to 12 ports in Local Device
1 = select hi limit
0 = select low limit
Bit[12]
Bit[24:13]
Reserved
Rp_Hi_Low Sel
Selection for Low or High Limit of Buffer Counter for Remote
device 13 bits maps to 13 ports in Remote Device
1 = select hi limit
0 = select low limit
Bit[31:25]
Reserved
18.2.5 Queue Management Register
18.2.5.1 CINQ - CPU Input Queue
Access:
Address:
Non-Zero-Wait-State,
h708
Direct Access,
Write only
Note:
Check IQ_RDY=1 in DCR3 (Interface Status Register) before writing into CPU Input Queue.
18.2.5.2 COTQ - CPU Output Queue
Access:
Address:
Non-Zero-Wait-State,
h70C
Direct Access,
Read only
Bit [30:0]
Bit [31]
31-bit CPU Output Queue Entry
Status queue is ready
31
19
10
9
0
Hi Limit
Low Limit
31
25
24
13
12
11
0
Rp_Hi_Low Sel
Lp_Hi_Low Sel
31
0
32-bit data from CPU input queue
31
30
0
CPU Output Queue Entry
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