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參數(shù)資料
| 型號(hào)： | MDS212CG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 12-Port 10/100Mbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA456 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456 |
| 文件頁(yè)數(shù)： | 71/111頁(yè) |
| 文件大?。?/td> | 1609K |
| 代理商： | MDS212CG |
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MDS212
Data Sheet
71
Zarlink Semiconductor Inc.
18.2.2 Interrupt Control Registers
Four 32-bit Control Registers.
ISR
Interrupt Status Register Identify the unmasked interrupt request sources
Access:
Zero-Wait-State,
Direct Access,
Address:
h7E0
ISRM
Masked Interrupt Status Reg.
masking
Access:
Zero-Wait-State,
Address:
h7E4
IMSK
Interrupt Mask Register
masked
Access:
Non-Zero-Wait-State,
Set bits to 1 to mask the corresponding interrupt sources
Address:
h7E8
IAR
Interrupt Acknowledgment Reg.
Access:
Non-Zero-Wait-State,
Set bits to 1 to clear the corresponding interrupt sources
Address:
h7EC
Read only
Identify the sources of interrupt with
Direct Access,Read only
Defines the interrupt sources to be
Direct Access,Write/Read
Clear the interrupt request bits
Direct Access,Write only
All 4 registers have a common register format and bit assignment
Interrupt MAC port mapping bit/port Interrupt Source
Interrupt Sources (The following bits need to be redefined.)
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Bit [8]
Bit [9]
Bit [10]
CPU_Q_Out
BSR
Double R
FCB_Low
HISC_BP
Reserved
Reserved
MAIL_ARR
HISC_TO
Reserved
FML_Av
CPU output queue level interrupt
Bad switch response
Double Release
FCB Low
HISC instruction pointer matched with Breakpoint Register
Mail arrived from HISC
HISC Timeout Interrupt
Link manager informs CPU that at least 16 Free Mail entry
available after CPU encounters empty Free Mail list situation.
Interrupt from MAC ports
Bit [11] for Port 0, Bit [12] for Port 1 … Bit [23] for port 12.
Search Engine found looped MCT Chain.
Bit [23:11]
MAC_PORT
Bit [24]
Bit [31:25] Reserved
MCT
Note:
MAIL_ARR, CPU_Q_Out, and interrupts cannot be cleared by the CPU. They will be cleared whenever their
queues are emptied.
31
25 24
23
11 10 9
8
7
6
5
4
3
2
1
0
MCT
MAC_Port Interrupt
FML
MAIL
BP
FCBL
DBR
BSR
CPQ
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