參數(shù)資料
型號(hào): MDS212CG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: 12-Port 10/100Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA456
封裝: 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456
文件頁數(shù): 91/111頁
文件大?。?/td> 1609K
代理商: MDS212CG
MDS212
Data Sheet
91
Zarlink Semiconductor Inc.
Usage
: These masks are used to prevent flooded or multicast packets from being transmitted out with more
than one port on a trunk. The Trunking Hash Key is used to select the proper mask (for load distribution). The
mask value will be set up to mask off all but one port within each trunk group.
18.2.11.4 IPMCAS - IP Multicast MAC Address Signature
Usage:
For following four registers IPMCAS0, IPMCAS1, IPMCMSK0 and IPMCMSK1, are used to distinguish
between IP multicast traffic and regular multicast. The MAC for IP multicast are h”01:00:5e:00:00:00” to h”
01:00:5e:7f:ff:ff” And the MASK for IPMC is: h“ff:ff:ff:80:00:00”.
The 6-byte of IP multicast MAC Address is stored in two 32-bit registers
IPMCAS0
IP Multicast MAC Address Byte [3:0]
Address:
h5E8
IPMCAS1
IP Multicast MAC Address Byte [5:4]
Address:
h5EC
Access:
Non-Zero-Wait-State,
Direct Access, Write/Read
These two registers define the MAC address signature of IP multicast.
Default = h” 01:00:5e:7f:ff:ff”
18.2.11.5 IPMCMSK - IP Multicast MAC Address Mask
The 6-byte of IP multicast MAC Mask is stored in two 32-bit registers
IPMCAS0 IP Multicast MAC Mask Byte [3:0]
Address:
h5F0
IPMCAS1 IP Multicast MAC Mask Byte [5:4]
Address:
h5F4
Access:
Non-Zero-Wait-State,
Direct Access, Write/Read
These two registers define the MAC Mask of IP multicast.
Default = h“ff:ff:ff:80:00:00”.
18.2.11.6 CFCBHDL - FCB Handle Register For CPU Read
Access:
Address:
Non-Zero-Wait-State,Direct Access,Read only
h580
Usage:
When CPU requests a free FDB to write a frame, it must request a free FCB via this register. The register
contains a free handle of FCB, which also pointer to a free FDB.
CPU reads FCB Handle: (When the CPU write FDB, it requires a FDB handle first).
CPU checks CFCBHDL[31],H_RDY ready or not. If so, CPU gets the FCB Handle from CFCBHDL[9:0]
31
24
23
16
15
8
7
0
IPMCAS0
MAC 3
MAC 2
MAC 1
MAC 0
IPMCAS1
MAC 5
MAC 4
31
24
23
16
15
8
7
0
IPMCMSK0
MASK 3
MASK 2
MASK 1
MASK 0
IPMCMSK1
MASK 5
MASK 4
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