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參數(shù)資料
| 型號： | MD80C52EXXX-16SBD |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 26/198頁 |
| 文件大?。?/td> | 4822K |
| 代理商： | MD80C52EXXX-16SBD |
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121
8111C–MCU Wireless–09/09
AT86RF231
9.7
Frequency Synthesizer (PLL)
The main PLL features are:
Generate RX/TX frequencies for all IEEE 802.15.4 - 2.4 GHz channels
Autonomous calibration loops for stable operation within the operating range
Two PLL-interrupts for status indication
Fast PLL settling to support frequency hopping
9.7.1
Overview
The PLL generates the RF frequencies for the AT86RF231. During receive operation the fre-
quency synthesizer works as a local oscillator on the radio transceiver receive frequency, during
transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the
RF transmit signal. The frequency synthesizer is implemented as a fractional-N PLL.
Two calibration loops ensure correct PLL functionality within the specified operating limits.
9.7.2
RF Channel Selection
The PLL is designed to support 16 channels in the 2.4 GHz ISM band with a channel spacing of
5 MHz according to IEEE 802.15.4. The center frequency of these channels is defined as
follows:
F
c = 2405 + 5 (k - 11) in [MHz], for k = 11, 12,..., 26
where k is the channel number.
The channel k is selected by register bits CHANNEL (register 0x08, PHY_CC_CA).
9.7.3
Frequency Agility
When the PLL is enabled during state transition from TRX_OFF to PLL_ON, the settling time is
typically t
TR4 = 110 s, including settling of the analog voltage regulator (AVREG) and PLL self
calibration, refer to Table 7-2 on page 43 and Figure 13-13 on page 168. A lock of the PLL is
indicated with an interrupt IRQ_0 (PLL_LOCK).
Switching between 2.4 GHz ISM band channels in PLL_ON or RX_ON states is typically done
within t
TR20 = 11 s. This makes the radio transceiver highly suitable for frequency hopping
applications.
When starting the transmit procedure the PLL frequency is changed to the transmit frequency
within a period of t
TR23 = 16 s before starting the transmission. After the transmission the PLL
settles back to the receive frequency within a period of t
TR24 = 32 s. This frequency step does
not generate an interrupt IRQ_0 (PLL_LOCK) or IRQ_1 (PLL_UNLOCK) within these periods.
9.7.4
Calibration Loops
Due to variation of temperature, supply voltage and part-to-part variations of the radio trans-
ceiver the VCO characteristics may vary.
To ensure a stable operation, two automated control loops are implemented, center frequency
(CF) tuning and delay cell (DCU) calibration. Both calibration loops are initiated automatically
when the PLL is enabled during state transition from TRX_OFF to PLL_ON state. Additionally,
center frequency calibration is initiated when the PLL changes to a different channel center
frequency.
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