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參數(shù)資料
| 型號(hào)： | MD80C52EXXX-16SBD |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 21/198頁(yè) |
| 文件大?。?/td> | 4822K |
| 代理商： | MD80C52EXXX-16SBD |
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117
8111C–MCU Wireless–09/09
AT86RF231
To calculate the total load capacitance, the following formula can be used:
C
L = 0.5 * (CX + CTRIM + CPAR).
The trimming capacitors provide the possibility of reducing frequency deviations caused by pro-
duction process variations or by external components tolerances. Note that the oscillation
frequency can only be reduced by increasing the trimming capacitance. The frequency deviation
caused by one step of C
TRIM decreases with increasing crystal load capacitor values.
An amplitude control circuit is included to ensure stable operation under different operating con-
ditions and for different crystal types. Enabling the crystal oscillator in P_ON state and after
leaving SLEEP state causes a slightly higher current during the amplitude build-up phase to
guarantee a short start-up time. At stable operation, the current is reduced to the amount neces-
sary for a robust operation. This also keeps the drive level of the crystal low.
Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects
caused by external component variations or by variations of board and circuit parasitics. On the
other hand, a larger crystal load capacitance results in a longer start-up time and a higher steady
state current consumption.
9.6.3
External Reference Frequency Setup
When using an external reference frequency, the signal must be connected to pin 26 (XTAL1) as
indicated in Figure 9-8 on page 117 and the register bits XTAL_MODE (register 0x12,
XOSC_CTRL) need to be set to the external oscillator mode. The oscillation peak-to-peak ampli-
tude shall be between 100 mV and 500 mV, the optimum range is between 400 mV and 500 mV.
Pin 25 (XTAL2) should not be wired.
Figure 9-8.
Setup for Using an External Frequency Reference
9.6.4
Master Clock Signal Output (CLKM)
The generated reference clock signal can be fed to a microcontroller using pin 17 (CLKM). The
internal 16 MHz raw clock can be divided by an internal prescaler. Thus, clock frequencies of
16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 250 kHz, or 62.5 kHz can be supplied by pin CLKM.
The CLKM frequency, update scheme, and pin driver strength is configurable using register
0x03 (TRX_CTRL_0). There are two possibilities how a CLKM frequency change gets effective.
If CLKM_SHA_SEL = 0 and/or CLKM_CTRL = 0, changing the register bits CLKM_CTRL imme-
diately affects the CLKM clock rate. Otherwise (CLKM_SHA_SEL = 1 and CLKM_CTRL > 0
before changing the register bits CLKM_CTRL) the new clock rate is supplied when leaving the
SLEEP state the next time.
To reduce power consumption and spurious emissions, it is recommended to turn off the CLKM
clock when not in use or to reduce its driver strength to a minimum, refer to Section 1.3 “Digital
XTAL2
XTAL1
AT86RF231
PCB
16 MHz
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| MR80C52XXX-20:R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C32E-30/883 | 8-BIT, 30 MHz, MICROCONTROLLER, CQFP44 |
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