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參數(shù)資料
| 型號(hào)： | MD80C52EXXX-16SBD |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 11/198頁(yè) |
| 文件大?。?/td> | 4822K |
| 代理商： | MD80C52EXXX-16SBD |
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108
8111C–MCU Wireless–09/09
AT86RF231
9.3.2
User accessible Frame Content
The AT86RF231 supports an IEEE 802.15.4 compliant frame format as shown in Figure 9-4 on
Figure 9-4.
AT86RF231 Frame Structure
Notes:
1. Stored into Frame Buffer for TX operation
2. Stored into Frame Buffer during frame reception.
A frame comprises two sections, the radio transceiver internally generated SHR field and the
user accessible part stored in the Frame Buffer. The SHR contains the preamble and the SFD
field. The variable frame section contains the PHR and the PSDU including the FCS, see Sec-
The Frame Buffer content differs depending on the direction of the communication (receive or
transmit). To access the data follow the procedures described in Section 6.2.2 “Frame Buffer
During frame reception, the payload and the link quality indicator (LQI) value of a successfully
received frame are stored in the Frame Buffer. The radio transceiver appends the LQI value to
the frame data after the last received octet. The frame length information is not stored in the
Frame Buffer. When using the Frame Buffer access mode to read the Frame Buffer content, the
frame length information is placed before the payload.
If the SRAM read access is used to read an RX frame, the frame length field (PHR) cannot be
accessed. The SHR (except the SFD used to generate the SHR) can generally not be read by
the microcontroller.
For frame transmission, the PHR and the PSDU needs to be stored in the Frame Buffer. The
PHR byte is the first byte in the Frame Buffer and must be calculated based on the PHR and the
PSDU. The maximum frame size supported by the radio transceiver is 128 bytes. If the
TX_AUTO_CRC_ON bit is set in register 0x05 (PHY_TX_PWR), the FCS field of the PSDU is
replaced by the automatically calculated FCS during frame transmission. That's why there is no
need to write the FCS field when using the automatic FCS generation.
To manipulate individual bytes of the Frame Buffer a SRAM write access can be used instead.
For non IEEE 802.15.4 compliant frames, the minimum frame length supported by the radio
transceiver is one byte (Frame Length Field + 1 byte of data).
Preamble Sequence
SFD
PHR(1)
Payload
LQI(2)
FCS
0
4
5
6
n + 3
n + 5
n + 6
Frame
Access
SHR not accesible
RX: Frame Buffer content
PHY generated
Length [octets]
Duration
4 octets / 128 s
1
n octets / n 32 s (n <= 128)
1
TX: Frame Buffer content
相關(guān)PDF資料 |
PDF描述 |
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| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C32E-36SC | 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44 |
| MR80C52XXX-20:R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C32E-30/883 | 8-BIT, 30 MHz, MICROCONTROLLER, CQFP44 |
| MR80C52CXXX-16/883R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MD80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MD80C862 | 制造商:Intel 功能描述:PROCESSOR:MICRO-PROCESSOR |
| MD80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MD80C86-2/883 | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:CPU 16BILT 5V CMOS 8MHZ 40CDIP - Bulk |
| MD80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube |
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