- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25635 > MD80C52EXXX-16SBD (ATMEL CORP) 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 PDF資料下載
參數(shù)資料
| 型號： | MD80C52EXXX-16SBD |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 10/198頁 |
| 文件大?。?/td> | 4822K |
| 代理商： | MD80C52EXXX-16SBD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁
107
8111C–MCU Wireless–09/09
AT86RF231
9.3
Frame Buffer
The AT86RF231 contains a 128 byte dual port SRAM. One port is connected to the SPI inter-
face, the other to the internal transmitter and receiver modules. For data communication, both
ports are independent and simultaneously accessible.
The Frame Buffer uses the address space 0x00 to 0x7F for RX and TX operation of the radio
transceiver and can keep one IEEE 802.15.4 RX or one TX frame of maximum length at a time.
Frame Buffer access modes are described in Section 6.6.2 “Register Description” on page 30.
Frame Buffer access conflicts are indicated by an under run interrupt IRQ_6 (TRX_UR). Note
that this interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame
Buffer. In that case the content of the Frame Buffer cannot be guaranteed.
Frame Buffer access is only possible if the digital voltage regulator is turned on. This is valid in
all device states except in SLEEP state. An access in P_ON state is possible if pin 17 (CLKM)
provides the 1 MHz master clock.
9.3.1
Data Management
Data in Frame Buffer (received data or data to be transmitted) remains valid as long as:
No new frame or other data are written into the buffer over SPI
No new frame is received (in any BUSY_RX state)
No state change into SLEEP state is made
No RESET took place
By default there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is
received during Frame Buffer read access of a previously received frame, interrupt IRQ_6
(TRX_UR) is issued and the stored data might be overwritten.
Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air
data rate. For a data rate of 250 kb/s a minimum SPI clock rate of 1 MHz is recommended.
Finally the microcontroller should check the transferred frame data integrity by an FCS check.
To protect the Frame Buffer content against being overwritten by newly incoming frames the
radio transceiver state should be changed to PLL_ON state after reception. This can be
achieved by writing immediately the command PLL_ON to register bits TRX_CMD (register
0x02, TRX_STATE) after receiving the frame, indicated by IRQ_3 (TRX_END).
Alternatively Dynamic Frame Buffer Protection can be used to protect received frames against
overwriting, for details refer to Section 11.8 “Dynamic Frame Buffer Protection” on page 154.
Both procedures do not protect the Frame Buffer from overwriting by the microcontroller.
In Extended Operating Mode during TX_ARET operation, see Section 7.2.4 “TX_ARET_ON -
Transmit with Automatic Retry and CSMA-CA Retry” on page 64, the radio transceiver switches
to receive, if an acknowledgement of a previously transmitted frame was requested. During this
period received frames are evaluated, but not stored in the Frame Buffer. This allows the radio
transceiver to wait for an acknowledgement frame and retry the frame transmission without writ-
ing them again.
A radio transceiver state change, except a transition to SLEEP state or a reset, does not affect
the Frame Buffer contents. If the radio transceiver is forced into SLEEP, the Frame Buffer is
powered off and the stored data gets lost.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C32E-36SC | 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44 |
| MR80C52XXX-20:R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C32E-30/883 | 8-BIT, 30 MHz, MICROCONTROLLER, CQFP44 |
| MR80C52CXXX-16/883R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MD80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MD80C862 | 制造商:Intel 功能描述:PROCESSOR:MICRO-PROCESSOR |
| MD80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MD80C86-2/883 | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:CPU 16BILT 5V CMOS 8MHZ 40CDIP - Bulk |
| MD80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 16BIT CMOS 8MHZ 40CDIP - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。