參數(shù)資料
型號: MCR705JP7CDWE
廠商: Freescale Semiconductor
文件頁數(shù): 92/164頁
文件大小: 0K
描述: MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 6KB(6K x 8)
程序存儲器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
33
Chapter 4
Interrupts
4.1 Introduction
An interrupt temporarily stops normal program execution to process a particular event. An interrupt does
not stop the execution of the instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the central processor unit (CPU)
registers on the stack and loads the program counter with a user-defined vector address.
4.2 Interrupt Vectors
Table 4-1 summarizes the reset and interrupt sources and vector assignments.
NOTE
If more than one interrupt request is pending, the CPU fetches the vector of
the higher priority interrupt first. A higher priority interrupt does not actually
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
MOR
Control
Bit
Global
Hardware
Mask
Local
Software
Mask
Priority
(1 = Highest)
Vector
Address
Reset
Power-on logic
RESET pin
Low-voltage reset
Illegal address reset
1
$1FFE–$1FFF
COP watchdog
COPEN(1)
Software
interrupt (SWI)
User code
Same priority
as instruction
$1FFC–$1FFD
External
interrupt (IRQ)
IRQ/VPP pin
I bit
IRQE bit
2
$1FFA–$1FFB
PA3 pin
PA2 pin
PA1 pin
PA0 pin
PIRQ(2)
Core timer
interrupts
TOF bit
RTIF bit
—I bit
TOFE bit
RTIE bit
3
$1FF8–$1FF9
Programmable
timer interrupts
ICF bit
OCF bit
TOF bit
—I bit
ICIE bit
OCIE bit
TOIE bit
4
$1FF6–$1FF7
Serial interrupt
SPIF bit
I bit
SPIE bit
5
$1FF4–$1FF5
Analog interrupt
CPF1 bit
CPF2 bit
I bit
CPIE bit
6
$1FF2–$1FF3
1. COPEN enables the COP watchdog timer.
2. PIRQ enables port A external interrupts on PA0–PA3.
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