參數(shù)資料
型號： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 122/164頁
文件大小： 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Parallel Input/Output
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
60
Freescale Semiconductor
7.3.4 Port B Logic
All port B pins have the general I/O port logic similar to port A; but they also share this function with inputs
or outputs from other modules, which are also attached to the pin itself or override the general I/O
function. PB0, PB1, PB2, and PB3 simply share their inputs with another module. PB4, PB5, PB6, and
PB7 will have their operation altered by outputs or controls from other modules.
7.3.5 PB0, PBI, PB2, and PB3 Logic
The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and PB3 pins of port B. When these
port B pins are programmed as an output, reading the port bit actually reads the value of the data latch
and not the voltage on the pin itself. When these port B pins are programmed as an input, reading the port
bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its
DDRB bit. The operations of the PB0–PB3 pins are summarized in Table 7-2.
Figure 7-8. PB0–PB3 Pin I/O Circuit
The PB0–PB3 pins share their inputs with another module. When using the other attached module, these
conditions must be observed:
1.
If the DDRB configures the pin as an output, then the port data register can provide an output which
may conflict with any external input source to the other module. The pulldown device will be
disabled in this case.
2.
If the DDRB configures the pin as an input, then reading the port data register will return the state
of the input in terms of the digital threshold for that pin (analog inputs will default to logic states).
3.
If DDRB configures the pin as an input and the pulldown device is activated for a pin, it will also
load the input to the other module.
4.
If interaction between the port logic and the other module is not desired, the pin should be
configured as an input by clearing the appropriate DDRB bit. The input pulldown device is disabled
by clearing the appropriate PDRB bit (or by disabling programmable pulldowns with the SWPDI bit
in the MOR).
PORT BDATA
REGISTER
BIT PBx
DATA DIRECTION
REGISTER B
BIT DDRBx
PULLDOWN
REGISTER B
BIT PDIBx
R
PBx
ANALOG SUBSYSTEM,
AND PROGRAMMABLE
TIMER INPUT CAPTURE
READ $0005
WRITE $0001
READ $0001
WRITE $0011
PULLDOWN
DEVICE
RESET
INTERNA
LD
AT
A
B
U
S
(PINS PB0, PB1, PB2, PB3)
WRITE $0005
SWPDI
MASK OPTION REG. ($1FF1)
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