參數(shù)資料
型號(hào)： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 8/164頁
文件大小： 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲(chǔ)器容量： 6KB（6K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
105
Chapter 11
Programmable Timer
11.1 Introduction
The MC68HC705JJ7/MC68HC705JP7 MCU contains a 16-bit programmable timer with an input capture
function and an output compare function as shown by the block diagram in Figure 11-1.
The basis of the capture/compare timer is a 16-bit free-running counter which increases in count with
every four internal bus clock cycles. The counter is the timing reference for the input capture and output
compare functions. The input capture and output compare functions provide a means to latch the times
at which external events occur, to measure input waveforms, and to generate output waveforms and
timing delays. Software can read the value in the 16-bit free-running counter at any time without affecting
the counter sequence.
The input/output (I/O) registers for the input capture and output compare functions are pairs of 8-bit
registers, because of the 16-bit timer architecture used. Each register pair contains the high and low bytes
of that function. Generally, accessing the low byte of a specific timer function allows full control of that
function; however, an access of the high byte inhibits that specific timer function until the low byte is also
accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four prescaler, the counter rolls
over every 262,144 internal clock cycles (every 524,288 oscillator clock cycles). Timer resolution with a
4-MHz crystal oscillator is 2 microseconds/count.
The interrupt capability, the input capture edge, and the output compare state are controlled by the timer
control register (TCR) located at $0012, and the status of the interrupt flags can be read from the timer
status register (TSR) located at $0013.
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