參數(shù)資料
型號： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 157/164頁
文件大小： 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Analog Subsystem
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
92
Freescale Semiconductor
8.7 Voltage Comparator Features
The two internal comparators can be used as simple voltage comparators if set up as described in
Table 8-8. Both comparators can be active in the wait mode and can directly restart the part by means of
the analog interrupt. Both comparators can also be active in the stop mode, but cannot directly restart the
part. However, the comparators can directly drive PB4 which can then be connected externally to activate
either a port interrupt on the PA0:3 pins or the IRQ/VPP pin.
8.7.1 Voltage Comparator 1
Voltage comparator 1 is always connected to two of the port B I/O pins. These pins should be configured
as inputs and have their software programmable pulldowns disabled. Also, the negative input of voltage
comparator 1 is connected to the PB3/AN3/TCAP and shared with the input capture function of the 16-bit
programmable timer. Therefore, the timer input capture interrupt should be disabled so that changes in
the voltage on the PB3/AN3/TCAP pin do not cause unwanted input capture interrupts.
The output of comparator 1 can be connected to the port logic driving the PB4/AN4/TCMP/CMP1 pin such
that the output of the comparator is ORed with the PB4 data bit and the OLVL bit from the 16-bit timer.
This capability requires that the OPT bit is set in the COPR at location $1FF0 as in Figure 8-12, and the
COE1 bit is set in the ASR at location $001E.
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by comparator 1 output to PB4 and voltage
offset capability to sample capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
Table 8-8. Voltage Comparator Setup Conditions
Comparator
Current
Source
Enable
Discharge
Device
Disable
Port B Pin
as Inputs
Port B Pin
Pulldowns
Disabled
Prog. Timer Input
Capture
Source
1
Not
affected
Not
affected
DDRB2 = 0
DDRB3 = 0
PDIB2 = 1
PDIB3 = 1
Not
affected
2
ISEN = 0
DDRB0 = 0
DDRB1 = 0
PDIB0 = 1
PDIB1 = 1
ICEN = 0
IEDG = 1
Address:
$1FF0
Bit 7
6
5
4321
Bit 0
Read:
EPMSEC
OPT
Write:
COPC
Reset:
U
UUUUUUU
= Unimplemented
U = Unaffected
Figure 8-12. COP and Security Register (COPR)
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