參數(shù)資料
型號： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 6/164頁
文件大?。?/td> 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Core Timer Counter Register
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
103
counting rate of the COP watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout
period and longest real-time interrupt period.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may
cause a real-time interrupt request to be missed or an additional real-time
interrupt request to be generated. Clear the COP timer just before changing
RT1 and RT0.
10.3 Core Timer Counter Register
A 15-stage ripple counter driven by a divide-by-eight prescaler is the basis of the core timer. The value of
the first eight stages is readable at any time from the read-only timer counter register as shown in
Power-on clears the entire counter chain and begins clocking the counter. After the startup delay (16 or
4064 internal bus cycles depending on the DELAY bit in the mask option register (MOR)), the power-on
reset circuit is released, clearing the counter again and allowing the MCU to come out of reset.
Each count of the timer counter register takes eight oscillator cycles or four cycles of the internal bus. A
timer overflow function at the eighth counter stage allows a timer interrupt every 2048 oscillator clock
cycles or every 1024 internal bus cycles.
10.4 COP Watchdog
Four counter stages at the end of the core timer make up the computer operating properly (COP)
watchdog which can be enabled by the COPEN bit in the MOR. The COP watchdog is a software error
detection system that automatically times out and resets the MCU if the COP watchdog is not cleared
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow
Interrupt Period
TOF = 1/(fOSC ÷ 2
11)
(Microseconds)
RT1
RT0
RTI
Rate
= fOSC
divided
by:
Real-Time
Interrupt Period
(RTI)
(Milliseconds)
COP Timeout Period
COP = 7-to-8 RTI Periods
(Milliseconds)
@ fOSC (MHz)
4.2
MHz
2.0
MHz
1.0
MHz
4.2
MHz
2.0
MHz
1.0
MHz
4.2 MHz
2.0 MHz
1.0 MHz
MinMax
488
1024
2048
00
215
7.80
16.4
32.8
54.6
62.4
115
131
229
262
01
216
15.6
32.8
65.5
109
125
229
262
459
524
10
217
31.2
65.5
131
218
250
459
524
918
1049
11
218
62.4
131
262
437
499
918
1049
1835
2097
Address:
$0009
Bit 7
654321
Bit 0
Read:
Bit 7
654321
Bit 0
Write:
Reset:
00000000
= Unimplemented
Figure 10-3. Core Timer Counter Register (CTCR)
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