參數(shù)資料
型號： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 100/164頁
文件大?。?/td> 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Interrupts
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
40
Freescale Semiconductor
4.7 Programmable Timer Interrupts
The 16-bit programmable timer can generate an interrupt whenever the following events occur:
Input capture
Output compare
Timer counter overflow
Setting the I bit in the condition code register disables timer interrupts. The controls for these interrupts
are in the timer control register (TCR) located at $0012 and in the status bits in the timer status register
(TSR) located at $0013.
4.7.1 Input Capture Interrupt
An input capture interrupt occurs if the input capture flag (ICF) becomes set while the input capture
interrupt enable bit (ICIE) is also set. The ICF flag bit is in the TSR, and the ICIE enable bit is located in
the TCR. The ICF flag bit is cleared by a read of the TSR with the ICF flag bit set, and then followed by a
read of the LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaffected by reset.
4.7.2 Output Compare Interrupt
An output compare interrupt occurs if the output compare flag (OCF) becomes set while the output
compare interrupt enable bit (OCIE) is also set. The OCF flag bit is in the TSR and the OCIE enable bit
is in the TCR. The OCF flag bit is cleared by a read of the TSR with the OCF flag bit set, and then followed
by an access to the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is
unaffected by reset.
4.7.3 Timer Overflow Interrupt
A timer overflow interrupt occurs if the timer overflow flag (TOF) becomes set while the timer overflow
interrupt enable bit (TOIE) is also set. The TOF flag bit is in the TSR and the TOIE enable bit is in the
TCR. The TOF flag bit is cleared by a read of the TSR with the TOF flag bit set, and then followed by an
access to the LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected by reset.
4.8 Serial Interrupts
The simple serial interface can generate the following interrupts:
Receive sequence complete
Transmit sequence complete
Setting the I bit in the condition code register disables serial interrupts. The controls for these interrupts
are in the serial control register (SCR) located at $000A and in the status bits in the serial status register
(SSR) located at $000B.
A transfer complete interrupt occurs if the serial interrupt flag (SPIF) becomes set while the serial interrupt
enable bit (SPIE) is also set. The SPIF flag bit is in the serial status register (SSR) located at $000B, and
the SPIE enable bit is located in the serial control register (SCR) located at $000A. The SPIF flag bit is
cleared by a read of the SSR with the SPIF flag bit set, and then followed by a read or write to the serial
data register (SDR) located at $000C. The SPIF flag bit can also be reset by writing a one to the SPIR bit
in the SCR.
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