參數(shù)資料
型號： MCR705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 138/164頁
文件大?。?/td> 0K
描述： MCU 8BIT 224B RAM 28-SOIC
標準包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 4x12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Analog Multiplex Register
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
75
Figure 8-4. INV Bit Action
NOTE
Either comparator may generate an output flag when the inputs are
exchanged due to a change in the state of the INV bit. It is therefore
recommended that the INV bit not be changed while waiting for a
comparator flag. Further, any changes to the state of the INV bit should be
followed by writing a logic 1 to both the CPFR1 and CPFR2 bits to clear any
extraneous CPF1 or CPF2 flags that may have occurred.
VREF
This read/write bit connects the channel select bus to VDD for making a reference voltage
measurement. It cannot be selected if any of the other input sources to the channel select bus are
selected as shown in Table 8-2. This bit is cleared by a reset of the device.
1 = Channel select bus connected to VDD if all MUX1:4 are cleared.
0 = Channel select bus cannot be connected to VDD.
MUX1:4
These are read/write bits that connect the analog subsystem pins to the channel select bus and voltage
comparator 2 for purposes of making a voltage measurement. They can be selected individually or
combined with any of the other input sources to the channel select bus as shown in Table 8-2.
NOTE
The VAOFF voltage source shown in Figure 8-1 depicts a small offset
voltage generated by the total chip current passing through the package
bond wires and lead frame that are attached to the single VSS pin. This
offset raises the internal VSS reference (AVSS) in the analog subsystem
with respect to the external VSS pin. Turning on the VSS MUX to the channel
select bus connects it to this internal AVSS reference line.
When making A/D conversions, this AVSS offset gets placed on the external
ramping capacitor since the discharge device on the PB0/AN0 pin
discharges the external capacitor to the internal AVSS line. Under these
circumstances, the positive input (+) to comparator 2 will always be higher
than the negative input (–) until the negative input reaches the AVSS offset
voltage plus any offset in comparator 2.
V–
V+
INV = 0
+
COMP
VIO
–
RISE
WHEN
V+ > V–
INV = 1
V+
V–
+
COMP
VIO
–
RISE
WHEN
V+ > V–
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