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System Integration Module (SIM)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
6-7
6.2.5
Power Management Register (PMR)
The power management register (PMR),
Figure 6-5, is used to control the various low-power options
including low-power sleep, low-power stop, and powering down individual on-chip modules.
11, 3
HWT,
HWTEN
Hardware watchdog timeout. This bit is set when the hardware watchdog timer has reached its
programmed timeout value. If HWTEN is also set, the bus cycle is terminated with an access error
exception.
10, 2
RPV,
RPVEN
Read protect violation. This bit is set when a read access is attempted to an area for which the chip select
is set to write only. If RPVEN is also set, the bus cycle is terminated with an access error exception.
9, 1
EXT,
EXTEN
External transfer error. This bit is set when an external transfer error is reported to the SIM on TEA. If
EXTEN is also set, the bus cycle is terminated with an access error exception.
8, 0
SUV,
SUVEN
Supervisor/user violation. This bit is set when a user mode access is attempted to an area for which the
chip select is set to supervisor only. If SUVEN is also set, the bus cycle is terminated with an access error
exception.
31
30
27
26
25
24
Field BDMPDN
—
ENETPDN
PLIPDN
DRAMPDN
Reset
0000_0000
R/W
R/W, Supervisor mode only
23
22
21
20
19
18
17
16
Field DMAPDN PWMPDN QSPIPDN TIMERPDN GPIOPDN
USBPDN
UART1PDN UART0PDN
Reset
0000_0000
R/W
R/W, Supervisor mode only
15
11
10
9
8
Field
—
USBWK
UART1WK
UART0WK
Reset
0000_0000
R/W
R/W, Supervisor mode only
76
5
4
3
0
Field
—
MOS
SLPEN
—
Reset
0000_0000
R/W
R/W, Supervisor mode only
Address
MBAR+0x008
Figure 6-5. Power Management Register (PMR)
Table 6-4. SPR Field Descriptions (continued)
Bits
Fields
Description