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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-26
Freescale Semiconductor
13.5.14 GCI Monitor Channel Transmit Abort Register (PGMTA)
All bits in this register are read/write and are cleared on hardware or software reset.
The PGMTA register contains the abort control bits for each of the four ports on the MCF5272 for the
transmit monitor channel.
76543
0
Field
AR3
AR2
AR1
AR0
—
Reset
0000_0000
R/W
Read/Write
Addr
MBAR + 0x372
Figure 13-26. GCI Monitor Channel Transmit Abort Register (PGMTA)
Table 13-9. PGMTA Field Descriptions
Bits
Name
Description
7
AR3
Abort request, port 3.
0 Default reset value.
1 Set by the CPU, this bit causes the monitor channel controller to transmit the end of message signal on the
E bit. Automatically cleared by the monitor channel controller on receiving an abort, that is, when PGMTS[AB]
is set.
6
AR2
Abort request, port 2. See AR3.
5
AR1
Abort request, port 1. See AR3.
4
AR0
Abort request, port 0. See AR3.
3–0
—
Reserved, should be cleared.