Universal Serial Bus (USB)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
12-30
Freescale Semiconductor
9. Interface #0 Descriptor
10. Endpoint #1 Descriptor
11. Configuration #3 Descriptor
12. Interface #0 Descriptor
13. Endpoint #1 Descriptor
14. Endpoint #2 Descriptor
12.3.4
USB Module Access Times
The access times for the USB module depend on whether the access is to a register, to an endpoint FIFO
(EPnDR register), or to the configuration RAM.
12.3.4.1
Registers
The USB module registers are accessed through the internal S-bus. Each register access takes 3 clock
cycles for reads and writes.
12.3.4.2
Endpoint FIFOs
The FIFO access time depends on the size, the time between accesses, and whether the previous FIFO
access was for the same endpoint. After a longword access to an endpoint’s FIFO, the next longword in
the FIFO is cached for a quicker access time on the next longword read. This mechanism is reset every
time another endpoint is accessed.
Table 12-19 shows the access times for the FIFOs.
12.3.4.3
Configuration RAM
The configuration RAM is longword accessible only. Access times for reads from the configuration RAM
are eight clock cycles per access. Clock cycle access times for back-to-back writes to the configuration
RAM are 3-5-5-5-5-5... Access times for writes separated by at least 1 clock cycle are 3-3-3-3-3-3…
Table 12-19. USB FIFO Access Timing
Access Type
Read
Write
Byte
5
4
Word
6
4
Long (back to back)
8-4-6-6-6-6...
4-6-6-6-6-6...
Long (1 clock gap)
8-3-5-5-5-5...
4-5-5-5-5-5...
Long (2 clock gap)
8-3-4-4-4-4...
4-4-4-4-4-4...
Long (3+ clock gap)
8-3-3-3-3-3...
4-4-4-4-4-4...