General Purpose I/O Module
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
17-7
Table 17-6 provides the same information as
Table 17-6, but organized by function instead of register field.
9–8
PBCNT4
Configure pin G3
00 PB4
01 URT0_CLK
1x Reserved
7–6
PBCNT3
Configure pin H3
00 PB3
01 URT0_RTS
1x Reserved
5–4
PBCNT2
Configure pin H2
00 PB2
01 URT0_CTS
1x Reserved
3–2
PBCNT1
Configure pin H1. The signal URT0_RxD is always internally connected to TIN2.
00 PB1
01 URT0_RxD/TIN2
1x Reserved
1–0
PBCNT0
Configure pin H4
00 PB0
01 URT0_TxD
1x Reserved
Table 17-6. Port B Control Register Function Bits
Pin Number
PBCNTxx = 00
(Function 0b00)
PBCNTxx = 01
(Function 0b01)
PBCNTxx = 10
(Function 0b10)
PBCNTxx = 11
(Function 0b11)
H4
PB0
URT0_TxD
—
H1
PB1
URT0_RxD/TIN2
—
H2
PB2
URT0_CTS
——
H3
PB3
URT0_RTS
——
G3
PB4
URT0_CLK
—
F3
PB5
TA
—
G4
PB6
—
M6
PB7
TOUT0
—
N8
PB8
E_TxD3
—
M8
PB9
E_TxD2
—
L8
PB10
E_TxD1
—
P9
PB11
E_RxD3
—
N9
PB12
E_RxD2
—
M9
PB13
E_RxD1
—
L9
PB14
E_RxER
—
P10
PB15
E_MDC
—
Table 17-5. PBCNT Field Descriptions (continued)
Bits
Name
Description (continued)