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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-12
Freescale Semiconductor
The above settings can be made by a single write of the 16-bit value 0x802B to PCSR.
The following restrictions should be observed when using the clock generator module:
The smallest multiplication factor is 2.
CLKIN should be significantly greater than (> 20 times) the synthesized clock.
PLIC block.
Figure 13-11. PLIC Internal Timing Signal Routing
Figure 13-12. PLIC Clock Generator
Port 0
Port 1
Port 2
Port 3
Prog Delay 0
Prog Delay 1
Prog Delay 2
DCL1
FSC1
Prog Delay 3
DFSC2
DCL1
DFSC2
DFSC3
DCL1/GDCL1_OUT
FSC1/FSR1/DFSC1
P1CR[M/S]
DCL0/URT1_CLK
PA8/FSC0/FSR0
GCI/IDL
DCL0
DFSC0
SFSC Gen
FSC0
FSC1
P1CR[FSM]
P0CR[M2-M0]
2-KHz to CPU
DFSC1
DFSC0
Pin
Mux 0
Pin
Mux 1
P0SDR[15:0]
P1SDR[15:0]
DFSC3
P2SDR[15:0]
P3SDR[15:0]
Mux
Multiply
Block
Divider
Block
Gen_FSC
GDCL
CKI[1:0]
CMULT[2:0]
FDIV[2:0]
DCL0/URT1_CLK
O192K
PA8/FSC0/FSR0