Queued Serial Peripheral Interface (QSPI) Module
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
14-11
Figure 14-5. SPI Modes Timing
14.5.2
QSPI Delay Register (QDLYR)
Table 14-4. QDLYR Field Descriptions
15
14
8
7
0
Field
SPE
QCD
DTL
Reset
0000_0100_0000_0100
R/W
Address
MBAR + 0x00A4
Figure 14-6. QSPI Delay Register (QDLYR)
Bits
Name
Description
15
SPE
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the
command RAM. Automatically cleared by the QSPI when a transfer completes.The user can also clear this
bit to abort transfer unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set
QWR[HALT].
14–8
QCD
QSPILCK Delay. When the DSCK bit in the command RAM, is set this field determines the length of the
delay from assertion of the chip selects to valid QSPI_CLK transition.
7–0
DTL
Delay after transfer.When the DT bit in the command RAM sets this field determines the length of delay
after the serial transfer.
SCK
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 1, CPHA = 1)