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Interrupt Controller
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
7-2
Freescale Semiconductor
Figure 7-1. Interrupt Controller Block Diagram
7.2
Interrupt Controller Registers
The interrupt controller register portion of the SIM memory map is shown in
Table 7-1.
All external interrupt inputs are edge sensitive, with the active edge being programmable through PITR.
An interrupt must remain asserted for at least three consecutive rising edges of CPU_ExtCLK to be
considered valid. The priority level of each interrupt source is programmed through the ICRs.
The MCF5272 does not support auto-vectored interrupts. Interrupt service routines for all interrupts should
have vectors in the user-defined interrupt region of the vector table (vectors 64–255). The location of these
vectors is programmable through the PIVR. For more information on the servicing of interrupts, see
Table 7-1. Interrupt Controller Registers
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x020
Interrupt control register 1 (ICR1)
[p. 7-4]
0x024
Interrupt control register 2 (ICR2)
[p. 7-5]
0x028
Interrupt control register 3 (ICR3)
[p. 7-5]
0x02C
Interrupt control register 4 (ICR4)
[p. 7-5]
0x030
Interrupt source register (ISR)
[p. 7-6]0x034
Programmable interrupt transition register (PITR)
[p. 7-8]0x038
Programmable interrupt wakeup register (PIWR)
[p. 7-9]0x03C
Reserved
Programmable interrupt
vector register (PIVR)
SYSTEM INTEGRATION MODULE (SIM)
Interrupt Controller
4 ICRs
PIWR
INT[1:6]
6
PIVR
PITR
ISR
Software
Watchdog
Four
Two UARTs
DMA
Ethernet
General-
Purpose
Timers
USB
QSPI
PLIC