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Universal Serial Bus (USB)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
12-17
12.3.2.13 USB Endpoint 0 Control Register (EP0CTL)
Figure 12-16 shows the USB endpoint 0 control register. provides both module level and endpoint 0
specific control (bits 0-9) functions.
Table 12-12 lists field descriptions for the USB endpoint 0 control register.
31
23
Field
—
Reset
0000_0000
R/W
22
19
18
17
16
Field
—
DEBUG
WOR_LVL
WOR_EN
Reset
0000_0000
R/W
15
14
13
12
11
10
9
8
Field
CLK_SEL
RESUME
AFE_EN
BUS_PWR USB_EN CFG_RAM_VAL CMD_ERR CMD_OVER
Reset
0000_0000
R/W
76
5
4
3
2
1
0
Field
CRC_ERR
—
OUT_LVL
IN_LVL
IN_DONE
—
Reset
0000_0000
R/W
Addr
MBAR + 0x104C
Figure 12-16. USB Endpoint 0 Control Register (EP0CTL)
Table 12-12. EP0CTL Field Descriptions
Bits
Name
Description
31–19
—
Reserved, should be cleared.
18
DEBUG
Debug mode. Enters debug mode. Debug mode enables CRC error generation and notification of
a change of address.
0 Normal operation
1 Enable debug mode functions
17
WOR_LVL
Wake-on-ring level select. Selects the active level of INT1 for the wake-on-ring function.
0 Wake-on-ring function is invoked when INT1 pin is 0.
1 Wake-on-ring function is invoked when INT1 pin is 1.
16
WOR_EN
Wake-on-ring enable. Generates a RESUME when the active level is detected on INT1 pin.
0 Wake-on-ring function disabled
1 Wake-on-ring function enabled
Note: the wake-on-ring function generates a RESUME only if the USB module is enabled for
remote wakeup by the host, for example, WAKE_ST = 1, and is suspended.
15
CLK_SEL
Clock source selection. Overrides the clock source for the USB module. If the USB_ExtCLK pin is
selected after reset, setting this bit forces the USB module to use the internal system clock.
0 Clock is retrieved from the clock selected at reset.
1 Clock is retrieved from the internal system clock.
Note: the selected clock must have a frequency of 48 MHz.