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Universal Serial Bus (USB)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
12-22
Freescale Semiconductor
12.3.2.15 USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0
Interrupt Registers (EP0ISR)
Figure 12-18 shows the USB endpoint 0 interrupt mask and general/endpoint 0 interrupt registers.
NOTE
Interrupt bits are reset by writing a 1 to the specified bits. Writing 0 has no
effect.
Table 12-14 lists field descriptions for the USB endpoint 0 interrupt mask and general/endpoint 0 interrupt
registers.
31
24
Field
—
Reset
0000_0000
R/W
23
17
16
Field
—
DEV_CFG
Reset
0000_0000
R/W
15
14
13
12
11
10
9
8
Field VEND_REQ
FRM_MAT
ASOF
SOF
WAKE_CHG
RESUME
SUSPEND
RESET
Reset
0000_0000
R/W
7654
3210
Field
OUT_EOT
OUT_EOP
OUT_LVL
IN_EOT
IN_EOP
UNHALT
HALT
IN_LVL
Reset
0000_0000
R/W
Addr
MBAR + 0x108C (EP0IMR); MBAR + 0x106C (EP0ISR)
Figure 12-18. USB Endpoint 0 Interrupt Mask (EP0IMR)
and General/Endpoint 0 Interrupt Registers (EP0ISR)
Table 12-14. EP0IMR and EP0ISR Field Descriptions
Bits
Name
Description
31–17
—
Reserved, should be cleared.
16
DEV_CFG
Device configuration change interrupt. Set when a device configuration change has been
received. The USB standard device requests SET_CONFIGURATION and SET_INTERFACE
generate a DEV_CFG interrupt. Any IN or OUT packets to the active endpoints cause a NAK
response to the host while this bit is set in order to allow the user to initialize the endpoints’
FIFO’s. Note that if one of these requests is done repeatedly and therefore the registers don’t
change, a DEV_CFG interrupt is still generated. If debug mode is enabled, a change in FAR also
generates an interrupt.
0 No interrupt pending
1 Device configuration change received