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Electrical Characteristics
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
23-6
Freescale Semiconductor
23.3.2
Processor Bus Input Timing Specifications
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the SDCLK output.
All other timing relationships can be derived from these values.
Table 23-7. Processor Bus Input Timing Specifications
Name
Characteristic1
1 All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.
0–66 MHz
Unit
Min
Max
Control Inputs
B1a 2
2 RSTI, TA, TEA, and INTx are synchronized internally. The setup time must be met only if recognition is needed on a particular
clock edge.
RSTI valid to SDCLK (setup)
6.5
—
nS
TA valid to SDCLK (setup)
8—
nS
TEA valid to SDCLK (setup)
8
—
nS
INTx valid to SDCLK (setup)
8
—
nS
BKPT valid to PSTCLK (setup)
10
—
nS
B1f
Mode selects (BUSW[1:0], WSEL, HiZ) valid to SDCLK (setup) (when RSTI asserted)
8
—
nS
B2d
SDCLK to asynchronous control inputs (RSTI, TA, TEA, INTx) invalid (hold)
2
—
nS
B2e
SDCLK to mode selects (BUSW[1,0], WSEL, HIZ) invalid (hold) (when RSTI asserted)
2
—
nS
B2f
PSTCLK to asynchronous control input BKPT invalid (hold)
0
—
nS
B3
RSTI width low
10T
—
nS
Data Inputs
B4
Data input (D[31:0]) valid to SDCLK (setup)
14
—
nS
B5
SDCLK to data input (D[31:0]) invalid (hold)
0
—
nS