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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-20
Freescale Semiconductor
13.5.8
Loopback Control Register (PLCR)
All bits in this register are cleared on hardware or software reset.
The PLCR is an 8-bit register containing the configuration information for all four ports on the MCF5272.
NOTE
In loopback mode, the respective port must be enabled (using
PnCR[ON/OFF]) along with the B1 and B2 channels (using PnCR[ENB1,
ENB2]) and the D channel (using PDRQR[DCNTI] when in IDL mode, for
instance). Also, if more than one of ports 1, 2, or 3 are programmed in
loopback mode, it is necessary to program the appropriate frame sync
13.5.9
Interrupt Configuration Registers (P0ICR–P3ICR)
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnICR registers contain interrupt configuration bits for each of the four ports on the MCF5272.
76543
210
Field
LM3
LM2
LM1
LM0
Reset
0000_0000
R/W
Read/Write
Addr
MBAR + 0x38F
Figure 13-20. Loopback Control Register (PLCR)
Table 13-3. PLCR Field Description
Bits
Name
Description
7-6
LM3
Loopback mode control, port 3.
00 Normal
01 Auto-echo
10 Local Loopback
11 Remote Loopback
5-4
LM2
Loopback mode control, port 2. See LM3.
3-2
LM1
Loopback mode control, port 1. See LM3.
1-0
LM0
Loopback mode control, port 0. See LM3.
15
14
12
11
10
9
8
7
6
5
4
3
2
1
0
PLCIR0–3 IE
—
GCR GCT GMR GMT
—
DTIE B2TIE B1TIE DRIE B2RIE B1RIE
Reset
0000_0000_0000_0000
R/W
Read/Write
Addr
MBAR + 0x0358 (P0ICR); 0x035A (P1ICR); 0x035C (P2ICR); 0x035E (P3ICR)
Figure 13-21. Interrupt Configuration Registers (P0ICR–P3ICR)