參數(shù)資料
型號(hào)： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 26/165頁
文件大小： 841K
代理商： MC68HC705PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
P-DECODER
MOTOROLA
REV 1.1
12-5
12.3.1 Clock Generator
76.8KHz clock signal feeds this clock generator. It generates the internal system
clock according to the DS1 and DS0 bits in the PDCR1 register.
12.3.2 BCH Corrector
Each codeword has 21 information bits, which correspond to the coefcients of a
polynomial having the terms from x30 down to x10. This polynomial is divided,
modulo-2, by the generating polynomial x10+x9+x8+x6+x5+x3+x1. The check bits
correspond to the coefcients of the terms from x9 to x0 in the remainder
polynomial found at the completion of this division. The complete block, consisting
of the information bits followed by the check bits, corresponds to the coefcients of
a polynomial which is integrally divisible in modulo-2 fashion by the generating
polynomial. Figure 12-3 shows the owchart of the BCH error detection and
correction. The BCH has the ability of correcting up to 2 bits error. The ERRF ag
in the PDSR register shows the error status. If ERRF = ‘0’, there are 2 or less than
2 bits error and the data in the RMIR register is valid. If ERRF = ‘1’, there are more
than 2 bits error and the data in the RMIR register is invalid.
Figure 12-3. BCH Decoder Flow Chart
START
S1 = 0
Error Function
S(x) = 0
N = 21
N = N+1
No
Yes
No
Yes
Receiving
Correct Digit
Yes
Syndrom generation
S3 = 0
No
Coefficient Calculation
N = 1
Yes
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