參數(shù)資料
型號： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 127/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
CLOCK DISTRIBUTION
MC68HC05PD6
8-4
REV 1.1
If OSC is selected as system clock source during STOP mode, CPU resumes
after the overow of POR counter and this overow also sets FTUP status ag.
If XOSC is selected as system clock source during STOP mode, no stop recovery
time is required for exiting STOP mode because XOSC never stops and re-start of
main oscillator depends on FOSCE bit.
During WAIT mode, only the CPU clocks are halted and the peripheral modules
are not affected. The WAIT mode is exited by the RESET and any interrupts.
8.4
TIME BASE
Time Base is a 14 bit up-counter which is clocked by XOSC input or OSC input
divided by 128. TBCLK bit in the TBCR1 register selects the clock source.
This 14 bit divider is initialized to $0078 only upon power on reset (POR). After
counting 8072 clocks, the STUP bit in the MISC register is set.
The divided clocks from the Time Base are used for LCDCLK, STUP, and COP.
Table 8-2. Recovery Time Requirements
BEFORE RESET OR INTERRUPT
POWER-ON
RESET
EXTERNAL
RESET
EXIT STOP
MODE BY
INTERRUPT
CPU CLK SOURCE
STOP
FOSCE
—
WAIT
—
OSC (OSC ON)
OUT
1
—
NO WAIT
—
OSC (OSC OFF)
OUT
0(1)
—
WAIT
—
IN
1
—
WAIT
IN(2)
0(2)
—
WAIT
XOSC (OSC ON)
OUT
1
—
NO WAIT
—
XOSC (OSC OFF)
OUT
0
—
WAIT
—
IN
1
—
WAIT
NO WAIT
IN
0
—
WAIT
NO WAIT
(1) This case has no meaning for applications.
(2) This case never occurs.
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