參數(shù)資料
型號(hào)： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 102/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
INTERRUPTS
MOTOROLA
REV 1.1
4-7
4.4.4 Timer Interrupt
Timer 1 and Timer 2 Interrupts share the same interrupt vector at $FFF4 and $FFF5.
Timer 1 contains three interrupt sources (TOI, ICI and OC1I) and Timer 2 contains two
interrupt sources (TI2I and OC2I). These interrupts are generated only if the
corresponding enable bit is set and the I bit of the CCR is cleared. See Section 9 for more
information on timer interrupts.
4.4.5 Serial Communication Interface (SCI)
The SCI interrupt use the vector at $FFF2 and $FFF3. The SCI interrupt occurs when one
of the interrupt flag bits in the serial communications status register is set, provided the I
bit in the CCR is clear and the enable bit in the serial communications control register 2
is set. Software in the serial interrupt service routine must determine the cause and priority
of the SCI interrupt by examining the interrupt flags and status bits in the SCI status
register. See Section 11 for more information on SCI interrupts.
4.4.6 Real Time Clock Interrupt (RTC)
The RTC interrupt is enabled when either RTCE, ALE or SECE bit in the control register
is set, provided the interrupt mask bit of the CCR is cleared. The interrupt service routine
address is specified by the contents of $FFF0 and $FFF1.
4.4.7 Interrupt Control Register (INTCR)
IRQ1E – Interrupt 1 Enable
IRQ1E bit enables IRQ1 interrupt when IRQ1F is set. This bit is cleared on
reset.
0 =
IRQ1 Interrupt is disabled
1 =
IRQ1 Interrupt is enabled
IRQ2E – Interrupt 2 Enable
IRQ2E bit enables IRQ2 interrupt when IRQ2F is set. This bit is cleared on
reset.
0 =
IRQ2 Interrupt is disabled
1 =
IRQ2 Interrupt is enabled
W
R
INTCR
$0008
reset
IRQ1E
0
7
00
54
0
0000
6
3210
IRQ2E
IRQ1S
IRQ2S
KWIE
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