參數(shù)資料
型號(hào)： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 16/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC05PD6
11-10
REV 1.1
11.9.4 Serial Communications Status Register (SCSR)
The serial communications status register (SCSR) provides inputs to the interrupt
logic circuits for generation of the SCI system interrupt. In addition, a noise ag bit
and a framing error bit are also contained in the SCSR.
TDRE
The transmit data register empty bit is set to indicate that the contents of the
serial communications data register have been transferred to the transmit serial
shift register. If the TDRE bit is clear, it indicates that the transfer has not yet
occurred and a write to the serial communications data register will overwrite
the previous value. The TDRE bit is cleared by accessing the serial
communications status register (with TDRE set), followed by writing to the
serial communications data register. Data can not be transmitted unless the
serial communications status register is accessed before writing to the serial
communications data register to clear the TDRE ag bit. Reset sets the TDRE
bit.
TC
The transmit complete bit is set at the end of a data frame, preamble, or break
condition if:
1.
TE = 1, TDRE = 1, and no pending data, preamble, or break is to be
transmitted; or
2.
TE = 0, and the data, preamble, or break (in the transmit shift register)
has been transmitted.
The TC bit is a status ag which indicates that one of the above conditions has
occurred. The TC bit is cleared by accessing the serial communications status
register (with TC set), followed by writing to the serial communications data
register. It does not inhibit the transmitter function in any way. Reset sets the TC
bit.
RDRF
When the receive data register full bit is set, it indicates that the receiver serial
shift register is transferred to the serial communications data register. If multiple
errors are detected in any one received word, the NF, FE, and RDRF bits will be
affected as appropriate during the same clock cycle. The RDRF bit is cleared
when the serial communications status register is accessed (with RDRF set)
followed by a read of the serial communications data register. Reset clears the
RDRF bit.
1
7
100000
-
6543210
W
R
SCSR
$000D
reset
TDRE
TC
RDRF
IDLE
OR
NF
FE
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