參數(shù)資料
型號： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 153/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
TIMER SYSTEM
MC68HC05PD6
9-16
REV 1.1
9.2.1 Timer Control Register 2 (TCR2)
TI2IE – Timer Input 2 Interrupt Enable
TI2IE bit enables Timer Input 2 (EVI) interrupt when TI2F is set. This bit is
cleared on reset.
0 =
Timer Input 2 Interrupt is disabled
1 =
Timer Input 2 Interrupt is enabled
OC2IE – Compare 2 Interrupt Enable
OC2IE bit enables Compare 2 (CMP2) interrupt when compare match is
detected (OC2F is set). This bit is cleared on reset.
0 =
Compare 2 Interrupt is disabled
1 =
Compare 2 Interrupt is enabled
T2CLK – Timer 2 Clock select
The T2CLK bit selects clock source for the timer counter 2. This bit is cleared
on reset.
0 =
CLK2 from prescaler is selected
1 =
EXCLK from EVI input block is selected
IM2 – Timer Input 2 Mode select
The IM2 bit selects whether EVI input is gated by CLK2 or not gated by CLK2.
This bit is cleared on reset.
0 =
EVI is not gated by CLK2 (Event Mode)
1 =
EVI is gated by CLK2 (Gated Mode)
IL2 – Timer Input 2 active edge (Level) select
The IL2 bit selects the active edge of EVI to increment counter for the Event
Mode (IM2 = 0), or gate enable level of EVI for the Gate Mode (IM2 = 1). This
bit is cleared on reset.
0 =
Falling edge is selected (Event Mode)
Low level enables counting (Gate Mode)
1 =
Rising edge is selected (Event Mode)
High level enables counting (Gated Mode)
IM2
IL2
Action on Clock
0
EVI falling edge increments counter
0
1
EVI rising edge increments counter
1
0
Low level on EVI enables counting
1
High level on EVI enables counting
W
R
TCR2
$0001C
reset
TI2IE
0
7
00
54
0
0000
6
3210
OC2IE
T2CLK
0
IM2
IL2
OL2
OE2
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