參數(shù)資料
型號(hào)： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 150/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
TIMER SYSTEM
MOTOROLA
REV 1.1
9-13
Figure 9-7. Timer 2 Block Diagram
The counter is incremented by the falling edge of the timer clock and the period
between two falling edges is dened as one timer cycle in the following
description.
The compare register (OC2) is provided for comparison with the timer counter 2
(CNT2). The OC2 data is transferred to the buffer register when the counter is
preset by a CPU write or by a compare output (CMP2). This buffer register is
compared with the timer counter 2 (CNT2).
The comparison between the counter and the OC2 buffer register is done when
the system clock high in each bus cycles. If counter matches with the OC2 buffer
register, the comparator latches this result during the current timer cycle. When
the next timer cycle begins, the comparator outputs CMP2 signal (if the compare
match is detected during previous timer cycle). This CMP2 is used in the counter
preset, data transfer to the buffer register, setting OC2F in the TSR2, and the EVO
block. The counter preset overrides the counter increment.
The OC2F bit may generate interrupt request if the OC2IE bit in the TCR2 is set.
COUNTER 2
COMPARATOR 2
REGISTER (OC2)
BUFFER 2
S
E
L
(TRANSFER)
($01)
0
1
COUNTER
WRITE
CLK2
EXCLK
T2CLK
CMP2
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