參數(shù)資料
型號： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 157/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
July 7, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05PD6
TIMER SYSTEM
MOTOROLA
REV 1.1
9-19
T2R1, T2R0 – Prescale Rate select bits for Timer 2
The T2R1 and T2R0 bits select prescale rate of CLK2 for Timer 2. These bits
are cleared on reset.
9.2.6 Timer Input 2 (EVI)
The Event Input (EVI) is used as an external clock input for Timer 2.
Figure 9-10. EVI Block Diagram
Since the external clock may be asynchronous to the internal clock, this input has
a synchronizer which samples external clock by the internal system clock. (The
input transition synchronizes to the falling edge of PH2. Therefore the minimum
pulse width for EVI must be larger than one system clock to be measured.)
The IM2 and IL2 bits in the TCR2 determine how this synchronized external clock
is used. IM2 bit decides between Event mode and Gated mode, and IL2 bit
decides which level or edge is activated.
In the Event mode (IM2 = 0), the external clock drives the Timer 2 counter directly
and the active edge at the EVI pin is selected by the IL2 bit. When active edge is
detected the TI2F bit in the TCR2 is set.
In the Gated mode (IM2 = 1), the EVI input is gated by CLK2 from the prescaler
and gate output drives the Timer 2 counter. IL2 bit decides active level of the
external input. When the transition from active level to inactive level is detected the
TI2F bit is set.
T2R1
T2R0
System clock divide by
00
1
01
4
10
32
1
256
PC4
EVI
SYNC
ACTIVE
EDGE/LEVEL
SELECTOR
GATE/EVENT
MODE
CONTROL
PC4
PH2
IL2
IM2
CLK2
to TI2F
EXCLK
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