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參數(shù)資料
| 型號(hào)： | MC145170 |
| 廠商： | Motorola, Inc. |
| 英文描述： | PLL Frequency Synthesizer(PLL頻率發(fā)生器) |
| 中文描述： | 鎖相環(huán)頻率合成器（PLL頻率發(fā)生器） |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 173K |
| 代理商： | MC145170 |
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3
MOTOROLA RF/IF APPLICATIONS INFORMATION
The basic phase detector is shown in Figure 4. HB3, HB4,
HB5 and HB6 all use the function shown in Figure 5. HB1 and
HB2 are behavioral implementations of a NOR gate
(Figure 6).
Figure 4.
Ref
Delay
50 ns
Delay
50 ns
DL2
DL1
HB3
v1Out
HB4
v1Out
HB6
HB5
v1Out
v2
v2
v1Out
v2
In2
In2
HB2
HB1
nor2
nor2
nor2
2
1
2
1
U4
U5
3
3
nor2
2
1
2
1
U2
U3
3
3
phiV
phiR
In
The circuit in Figure 5 performs both an AND operation
and an inverter operation in one function. When used as HB3
and HB4, the output of the delay element is inverted and
ANDed with the undelayed input. The result is a pulse whose
width is equal to the value of the delay. As HB5 and HB6, the
input signal (In or Ref), is inverted and compared with the
corresponding pulse to determine if it leads or lags.
Figure 5.
v1
v1
v2
v2
Out
IF (V(v1)
≥
1 & V(v2) < 1, 5, 0)
The output of HB3 is a pulse occurring at the rising edge of
the Reference clock input. The output of HB4 is a similar
pulse occurring at the rising edge of In. HB6 compares the
output pulse of HB3 with In to determine if it leads In. If Ref
leads In, then HB6 will generate a pulse at its output. If Ref
lags In, the output of HB6 will be zero. In the same manner,
HB5 generates a pulse when In leads Ref.
An RS flip–flop is used to generate the lead and lag
pulses. HB6 sets the RSFF U2/U3 and the output of HB4
resets the RSFF. The output of U3 is a pulse whose width
equals the amount of lead of Ref over In. HB4 outputs a pulse
for each cycle of In and resets the RSFF to 0, terminating the
pulse and holding the output of U3 at 0 for conditions where
Ref does not lead In.
Figure 6.
In1
In1
In2
In2
Out
IF (V(In1)
≥
1 | V(In2)
≥
1, 0, 5)
The RSFF formed by U4/U5 performs the same function
for In leading Ref. When In leads Ref, HB5 generates a pulse
setting the U4, U5 RSFF. HB3 resets this FF coincident with
the rising edge of Ref.
To fully emulate the operation of the MC145170 phase
detector, the pulses must be present in the output. This is the
purpose of HB1 and HB2. By adding the corresponding pulse
to the outputs of the RSFFs, the operation of the phase
detector has been emulated.
For best performance, the output of the phase detector
model should look like the output of the phase detector in the
MC145170. This can be accomplished by adding transistor
models that represent those used in the MC145170. For
applications using the PhiR and PhV outputs, Figure 7 can be
used. For applications using PDout, use the circuit shown in
Figure 8.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145170D1 | 制造商: 功能描述: 制造商:Motorola Inc 功能描述: 制造商:undefined 功能描述: |
| MC145170D2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170D2R2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170DT2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170DT2R2 | 功能描述:IC SERIAL PLL FREQ SYNTH 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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