參數(shù)資料
型號(hào)： MC14517
廠商： ON SEMICONDUCTOR
英文描述： Dual 64-Bit Static Shift Register
中文描述： 雙64位靜態(tài)移位寄存器
文件頁(yè)數(shù)： 1/6頁(yè)
文件大?。?/td> 209K
代理商： MC14517
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
403
MC14517B
The MC14517B dual 64–bit static shift register consists of two identical,
independent, 64–bit registers. Each register has separate clock and write
enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data
input is entered by clocking, regardless of the state of the write enable input.
An output is disabled (open circuited) when the write enable input is high.
During this time, data appearing at the data input as well as the 16–bit,
32–bit, and 48–bit taps may be entered into the device by application of a
clock pulse. This feature permits the register to be loaded with 64 bits in 16
clock periods, and also permits bus logic to be used. This device is useful in
time delay circuits, temporary memory storage circuits, and other serial shift
register applications.
Diode Protection on All Inputs
Fully Static Operation
Output Transitions Occur on the Rising Edge of the Clock Pulse
Exceedingly Slow Input Transition Rates May Be Applied to the Clock
Input
3–State Output at 64th–Bit Allows Use in Bus Logic Applications
Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
MAXIMUM RATINGS
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Iin, Iout
Input or Output Current (DC or Transient),
Value
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
10
Unit
V
V
mA
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
FUNCTIONAL TRUTH TABLE
(X = Don’t Care)
Write
Enable
Data
16–Bit Tap
0
0
X
Content of 16–Bit
Clock
32–Bit Tap
Content of 32–Bit
Displayed
High Impedance
Content of 32–Bit
Displayed
High Impedance
Content of 32–Bit
Displayed
Data at tap
entered into 33–Bit
Content of 32–Bit
Displayed
High Impedance
48–Bit Tap
Content of 48–Bit
Displayed
High Impedance
Content of 48–Bit
Displayed
High Impedance
Content of 48–Bit
Displayed
Data at tap
entered into 49–Bit
Content of 48–Bit
Displayed
High Impedance
64–Bit Tap
Content of 64–Bit
Displayed
High Impedance
Content of 64–Bit
Displayed
High Impedance
Content of 64–Bit
Displayed
High Impedance
Displayed
High Impedance
Content of 16–Bit
Displayed
High Impedance
Content of 16–Bit
Displayed
Data at tap
entered into 17–Bit
Content of 16–Bit
Displayed
High Impedance
0
1
1
0
X
X
1
1
0
X
Data entered
into 1st Bit
Data entered
into 1st Bit
X
1
0
Content of 64–Bit
Displayed
High Impedance
1
X
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
CB
WEB
Q48B
Q16B
VDD
DB
Q32B
Q64B
CA
WEA
Q48A
Q16A
VSS
Q32A
DA
Q64A
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